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    Single clock reference for compressed domain processing systems
    2.
    发明授权
    Single clock reference for compressed domain processing systems 失效
    用于压缩域处理​​系统的单时钟参考

    公开(公告)号：US06356212B1

    公开(公告)日：2002-03-12

    申请号：US09506612

    申请日：2000-02-18

    申请人： Paul Wallace Lyons ,  Alfonse Anthony Acampora ,  John Prickett Beltz ,  Victor Vincent D'Alessandro ,  Clifford Arthur Pecota

    发明人： Paul Wallace Lyons ,  Alfonse Anthony Acampora ,  John Prickett Beltz ,  Victor Vincent D'Alessandro ,  Clifford Arthur Pecota

    IPC分类号： H03M700

    CPC分类号： H04N21/4302 ,  H04N7/52 ,  H04N21/242 ,  H04N21/4305

    摘要： A device and method for utilizing a single clock signal to generate a digital data stream signal for transmission in a compressed domain transmission system. The device includes a plurality of packetized elementary stream encoders electronically coupled to a transport stream encoder electronically coupled to an output interface adapted to generate the digital data stream signal. The method includes: operating each of the packetized elementary stream encoders responsively to the single clock sequence to generate a plurality of packetized elementary stream signals; operating the transport stream encoder responsively to the single clock signal to form a transport stream signal from the plurality of packetized elementary stream signals, wherein the transport stream signal includes a plurality of data packets each formed using the transport stream encoder and select ones of the plurality of data packets formed by the transport stream encoder include synchronization data; and, operating the output interface responsively to the single clock reference to output the digital data stream signal in compliance with an predefined manner.

    摘要翻译： 一种用于利用单个时钟信号产生用于在压缩域传输系统中传输的数字数据流信号的装置和方法。 该设备包括电子耦合到传输流编码器的多个分组化的基本流编码器，电子耦合到适于生成数字数据流信号的输出接口。 该方法包括：响应于单个时钟序列操作每个分组化的基本流编码器以产生多个分组化的基本流信号; 响应于单个时钟信号操作传输流编码器以形成来自多个分组化的基本流信号的传输流信号，其中传输流信号包括多个数据分组，每个数据分组使用传输流编码器形成，并且选择多个 由传输流编码器形成的数据分组包括同步数据; 并且响应于单个时钟参考来操作输出接口以按照预定义的方式输出数字数据流信号。

    Flow control, latency control, and bitrate conversions in a timing correction and frame synchronization apparatus
    3.
    发明授权
    Flow control, latency control, and bitrate conversions in a timing correction and frame synchronization apparatus 有权
    时序校正和帧同步装置中的流控制，等待时间控制和比特率转换

    公开(公告)号：US06330286B1

    公开(公告)日：2001-12-11

    申请号：US09589775

    申请日：2000-06-08

    申请人： Paul Wallace Lyons ,  John Prickett Beltz ,  Alfonse Anthony Acampora

    发明人： Paul Wallace Lyons ,  John Prickett Beltz ,  Alfonse Anthony Acampora

    IPC分类号： H04N712

    CPC分类号： H04N21/23424 ,  H04N21/23406 ,  H04N21/23608 ,  H04N21/44004 ,  H04N21/44016

    摘要： In a compressed domain digital communications system, a method for reducing a variable latency associated with a buffer and at least partially resulting from at least one splice between a FROM bitstream and a TO bitstream each including data corresponding to a plurality of frames, the method including: selectively deleting data corresponding to a select at least one of the frames from the buffer based upon the variable latency so as to reduce the variable latency when an amount of data corresponding to a number of frames present in the buffer is greater than a given number of frames; and, regulating a flow of data in the system to prevent an underflow condition in the system by effecting a repeat last frame command and prevent an overflow condition in the system by slowing a rate of transmission for the data associated with at least one of the frames in the TO bitstream.

    摘要翻译： 在压缩域数字通信系统中，一种减少与缓冲器相关联的可变延迟并且至少部分地由FROM位流和TO位流之间的至少一个拼接产生的方法，每一个包含对应于多个帧的数据，该方法包括 基于所述可变延迟，有选择地从所述缓冲器中删除与所述缓冲器中的至少一个选择对应的数据，以便当与所述缓冲器中存在的帧的数量相对应的数据量大于给定数量时，减少所述可变等待时间 的框架 并且通过执行重复的最后帧命令来调节系统中的数据流以防止系统中的下溢状况，并通过减慢与至少一个帧相关联的数据的传输速率来防止系统中的溢出状况 在TO比特流中。