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    Single clock reference for compressed domain processing systems
    1.
    发明授权
    Single clock reference for compressed domain processing systems 失效
    用于压缩域处理​​系统的单时钟参考

    公开(公告)号：US06356212B1

    公开(公告)日：2002-03-12

    申请号：US09506612

    申请日：2000-02-18

    申请人： Paul Wallace Lyons ,  Alfonse Anthony Acampora ,  John Prickett Beltz ,  Victor Vincent D'Alessandro ,  Clifford Arthur Pecota

    发明人： Paul Wallace Lyons ,  Alfonse Anthony Acampora ,  John Prickett Beltz ,  Victor Vincent D'Alessandro ,  Clifford Arthur Pecota

    IPC分类号： H03M700

    CPC分类号： H04N21/4302 ,  H04N7/52 ,  H04N21/242 ,  H04N21/4305

    摘要： A device and method for utilizing a single clock signal to generate a digital data stream signal for transmission in a compressed domain transmission system. The device includes a plurality of packetized elementary stream encoders electronically coupled to a transport stream encoder electronically coupled to an output interface adapted to generate the digital data stream signal. The method includes: operating each of the packetized elementary stream encoders responsively to the single clock sequence to generate a plurality of packetized elementary stream signals; operating the transport stream encoder responsively to the single clock signal to form a transport stream signal from the plurality of packetized elementary stream signals, wherein the transport stream signal includes a plurality of data packets each formed using the transport stream encoder and select ones of the plurality of data packets formed by the transport stream encoder include synchronization data; and, operating the output interface responsively to the single clock reference to output the digital data stream signal in compliance with an predefined manner.

    摘要翻译： 一种用于利用单个时钟信号产生用于在压缩域传输系统中传输的数字数据流信号的装置和方法。 该设备包括电子耦合到传输流编码器的多个分组化的基本流编码器，电子耦合到适于生成数字数据流信号的输出接口。 该方法包括：响应于单个时钟序列操作每个分组化的基本流编码器以产生多个分组化的基本流信号; 响应于单个时钟信号操作传输流编码器以形成来自多个分组化的基本流信号的传输流信号，其中传输流信号包括多个数据分组，每个数据分组使用传输流编码器形成，并且选择多个 由传输流编码器形成的数据分组包括同步数据; 并且响应于单个时钟参考来操作输出接口以按照预定义的方式输出数字数据流信号。

    Flow control, latency control, and bitrate conversions in a timing correction and frame synchronization apparatus
    3.
    发明授权
    Flow control, latency control, and bitrate conversions in a timing correction and frame synchronization apparatus 有权
    时序校正和帧同步装置中的流控制，等待时间控制和比特率转换

    公开(公告)号：US06330286B1

    公开(公告)日：2001-12-11

    申请号：US09589775

    申请日：2000-06-08

    申请人： Paul Wallace Lyons ,  John Prickett Beltz ,  Alfonse Anthony Acampora

    发明人： Paul Wallace Lyons ,  John Prickett Beltz ,  Alfonse Anthony Acampora

    IPC分类号： H04N712

    CPC分类号： H04N21/23424 ,  H04N21/23406 ,  H04N21/23608 ,  H04N21/44004 ,  H04N21/44016

    摘要： In a compressed domain digital communications system, a method for reducing a variable latency associated with a buffer and at least partially resulting from at least one splice between a FROM bitstream and a TO bitstream each including data corresponding to a plurality of frames, the method including: selectively deleting data corresponding to a select at least one of the frames from the buffer based upon the variable latency so as to reduce the variable latency when an amount of data corresponding to a number of frames present in the buffer is greater than a given number of frames; and, regulating a flow of data in the system to prevent an underflow condition in the system by effecting a repeat last frame command and prevent an overflow condition in the system by slowing a rate of transmission for the data associated with at least one of the frames in the TO bitstream.

    摘要翻译： 在压缩域数字通信系统中，一种减少与缓冲器相关联的可变延迟并且至少部分地由FROM位流和TO位流之间的至少一个拼接产生的方法，每一个包含对应于多个帧的数据，该方法包括 基于所述可变延迟，有选择地从所述缓冲器中删除与所述缓冲器中的至少一个选择对应的数据，以便当与所述缓冲器中存在的帧的数量相对应的数据量大于给定数量时，减少所述可变等待时间 的框架 并且通过执行重复的最后帧命令来调节系统中的数据流以防止系统中的下溢状况，并通过减慢与至少一个帧相关联的数据的传输速率来防止系统中的溢出状况 在TO比特流中。

    Method and apparatus for time base recovery and processing
    6.
    发明授权
    Method and apparatus for time base recovery and processing 失效
    用于时基恢复和处理的方法和装置

    公开(公告)号：US06266384B1

    公开(公告)日：2001-07-24

    申请号：US08858634

    申请日：1997-05-19

    申请人： Alfonse Anthony Acampora ,  Victor Vincent D'Alessandro ,  Charles Martin Wine

    发明人： Alfonse Anthony Acampora ,  Victor Vincent D'Alessandro ,  Charles Martin Wine

    IPC分类号： H04L700

    CPC分类号： H04N21/4382 ,  H04N21/4307 ,  H04N21/8547

    摘要： An apparatus and method for receiving a bitstream containing timing information and respective program information, the program information is processed and associated with locally generated timing information to form an output bitstream, the locally generated timing information is synchronized to the received timing information so that the timing relationships of the received program information are preserved even after the program information is processed.

    摘要翻译： 一种用于接收含有定时信息和相应节目信息的比特流的装置和方法，处理节目信息并与本地生成的定时信息相关联以形成输出比特流，将本地生成的定时信息与接收到的定时信息同步， 即使在程序信息被处理之后，也保持所接收节目信息的关系。

    Transport processor interface for a digital television system
    7.
    发明授权
    Transport processor interface for a digital television system 失效
    数字电视系统的传输处理器接口

    公开(公告)号：US5903324A

    公开(公告)日：1999-05-11

    申请号：US750390

    申请日：1996-12-06

    申请人： Paul Wallace Lyons ,  Alfonse Anthony Acampora

    发明人： Paul Wallace Lyons ,  Alfonse Anthony Acampora

    IPC分类号： H04N7/32 ,  H04N7/54 ,  H04N21/6377 ,  H04N21/658 ,  H04N7/60

    CPC分类号： H04N21/658 ,  H04N19/152 ,  H04N21/6377 ,  H04N7/54 ,  H04N19/50

    摘要： A transmitted high definition television signal is represented by a packetized datastream configured as a sequence of data fields with a non-uniform data rate due to different types of different duration non-data overhead information. Each data field is prefaced by a Field Sync overhead segment followed by 312 packetized data segments each with associated overhead information. At a transmitter, a transport processor forms data packets with associated headers and exhibits uninterrupted operation at a constant uniform data rate, while supplying a packetized datastream to a network which constructs sequential data fields by inserting the non-data overhead information into the datastream. The transport processor is advantageously operated at a constant uniform data rate without having to modify the original data field structure to accommodate the needs of the data field construction network. This result is facilitated by transferring data from the transport processor to an associated interface/buffer network in response to a 3/8 symbol clock, in combination with a predetermined buffer fullness level. A counterpart transport processor/decoder at a receiver coacts with a data field processor and similarly exhibits uninterrupted operation at a constant uniform data rate.

    摘要翻译： PCT No.PCT / US95 / 07459 Sec。 371日期1996年12月6日第 102（e）日期1996年12月6日PCT提交1995年6月13日PCT公布。 出版物WO96 / 1996年1月11日发布的高分辨率电视信号由配置为由于不同类型的不同持续时间非数据开销信息而具有不均匀数据速率的数据字段序列的分组化数据流表示。 每个数据字段由字段同步开销段开始，后跟312个分组化的数据段，每个数据段具有相关的开销信息。 在发射机处，传输处理器形成具有关联报头的数据分组，并且以恒定的均匀数据速率展现不间断的操作，同时通过将非数据开销信息插入到数据流中来构建顺序数据字段的网络提供分组化的数据流。 运输处理器有利地以恒定的均匀数据速率运行，而不必修改原始数据场结构以适应数据场建设网络的需要。 通过结合预定的缓冲器充满度水平，将数据从传输处理器传送到相关的接口/缓冲器网络，从而有助于响应于+ E，fra 3/8 + EE符号时钟。 接收器处的对方传送处理器/解码器与数据场处理器共同作用并且以恒定的统一数据速率类似地显示不间断的操作。

    Synchronizing a packetized digital datastream to an output processor in a television signal processing system
    8.
    发明授权
    Synchronizing a packetized digital datastream to an output processor in a television signal processing system 失效
    将分组数字数据流与电视信号处理系统中的输出处理器同步

    公开(公告)号：US5847779A

    公开(公告)日：1998-12-08

    申请号：US750403

    申请日：1996-12-06

    申请人： Alfonse Anthony Acampora ,  Richard Michael Bunting ,  Paul Wallace Lyons

    发明人： Alfonse Anthony Acampora ,  Richard Michael Bunting ,  Paul Wallace Lyons

    IPC分类号： H04N7/32 ,  H04N7/62 ,  H04N7/64

    CPC分类号： H04N19/152 ,  H04N19/50

    摘要： A system of the present invention addresses the difficulty of aligning a reference sync byte at the beginning of a data packet during situations where the system experiences severe problems such as arbitrary resets/restarts or transmission disturbances. Specifically, the sync byte at the beginning of the data packet is automatically aligned with the beginning of a data acquisition interval when data is requested, even when there are arbitrary system resets/restarts. The alignment of the first data packet following a system reset is facilitated by the use of a Start Of Packet flag concurrent with the reference byte, together with a controlled logic network.

    摘要翻译： PCT No.PCT / US94 / 06803。 371日期1996年12月6日第 102（e）日期1996年12月6日PCT提交1994年6月15日PCT公布。 公开号WO95 / 34990 日期1995年12月21日本发明的系统解决了在系统经历诸如任意复位/重启或传输干扰之类的严重问题的情况下在数据分组开头处对准参考同步字节的困难。 具体地说，即使在任意的系统复位/重新启动时，数据包开始时的同步字节也自动与数据采集间隔的开始对齐。 通过与受控逻辑网络一起使用与参考字节并发的分组标志开始来促进系统复位之后的第一数据分组的对准。

    Apparatus for formatting a packetized digital datastream suitable for conveying television information
    9.
    发明授权
    Apparatus for formatting a packetized digital datastream suitable for conveying television information 失效
    用于格式化适于传送电视信息的打包数字数据流的装置

    公开(公告)号：US5831690A

    公开(公告)日：1998-11-03

    申请号：US750441

    申请日：1996-12-06

    申请人： Paul Wallace Lyons ,  Alfonse Anthony Acampora

    发明人： Paul Wallace Lyons ,  Alfonse Anthony Acampora

    IPC分类号： G06T9/00 ,  H04N7/66 ,  H04N21/2389 ,  H04N21/242 ,  H04N21/43 ,  H04N21/4385 ,  H04N7/04 ,  H04N7/12

    CPC分类号： G06T9/007 ,  H04N21/2389 ,  H04N21/242 ,  H04N21/4305 ,  H04N21/4385

    摘要： A transmission processor (16) receives an input packetized datastream (FIGS. 6-9; FIGS. 15-18 signal A) containing packets of data bytes including MPEG coded video information. The transmission processor outputs a symbol datastream (FIGS. 15-18 signal F) representing a sequence of data fields (FIG. 1) comprising groups of data segments (X) with an associated field sync segment. The transmission processor inserts overhead information. e.g., FEC error coding information, into each data segment, and inserts the longer duration field sync overhead segment between groups of data field segments. The frequency of the transmission processor input byte clock (SC/2, FIG. 6; FIG. 15) an integer sub-multiple of an output symbol clock (SC) frequency. The input datastream exhibits constant uniform inter-packet data gaps and a constant uniform data rate, thereby facilitating the seamless insertion of the field sync overhead segment into the datastream without interrupting the datastream. Similar but inverse processing occurs at a receiver.

    摘要翻译： 发送处理器（16）接收包含包含MPEG编码视频信息的数据字节分组的输入分组化数据流（图6-9;图15-18信号A）。 传输处理器输出表示包括具有相关联的字段同步段的数据段（X）组的数据字段序列（图1）的符号数据流（图15-18信号F）。 传输处理器插入开销信息。 例如FEC错误编码信息，并且在数据字段段的组之间插入较长持续时间的字段同步开销段。 传输处理器输入字节时钟（SC / 2，图6;图15）的频率是输出符号时钟（SC）频率的整数子倍。 输入数据流表现出恒定均匀的分组间数据间隙和恒定的均匀数据速率，从而有助于将场同步开销段无缝地插入到数据流中而不中断数据流。 在接收器处发生类似但是相反的处理。

    Transport processor interface and video recorder/playback apparatus in a field structured datastream suitable for conveying television information
    10.
    发明授权
    Transport processor interface and video recorder/playback apparatus in a field structured datastream suitable for conveying television information 失效

    公开(公告)号：US6081650A

    公开(公告)日：2000-06-27

    申请号：US750442

    申请日：1996-12-06

    申请人： Paul Wallace Lyons ,  Alfonse Anthony Acampora

    发明人： Paul Wallace Lyons ,  Alfonse Anthony Acampora

    IPC分类号： H04N7/32 ,  H04N7/54 ,  H04N21/236 ,  H04N21/434 ,  H04N5/76

    CPC分类号： H04N21/434 ,  H04N19/152 ,  H04N21/236 ,  H04N7/54 ,  H04N19/50

    摘要： A transmitted high definition television signal is represented by a packetized datastream configured as a sequence of data fields (FIG. 1) with a non-uniform data rate due to unequal inter-data overhead information intervals. Each data field is prefaced by a Field Sync overhead segment followed by 312 packetized data segments each with associated overhead information (FEC). At a transmitter (FIG. 33), a transport processor (14) forms data packets with associated headers and exhibits uninterrupted operation at a constant uniform data rate, while supplying a packetized datastream to a network (17) which constructs sequential data fields by inserting the non-data overhead information into the datastream. The transport processor is advantageously operated at a constant uniform data rate without having to modify the original data field structure to accommodate the needs of the data field construction network. This result is facilitated by transferring data from the transport processor to an associated interface/buffer network (46) in response to a 3/8 symbol clock, in combination with a predetermined buffer fullness level. Specifically, a video recorder/playback device (15) receives a constant uniform data rate packetized datastream from the transport processor, and outputs a constant uniform data rate datastream to the interface/buffer network. A counterpart transport processor/decoder (86) at a receiver (FIG. 34) coacts with a data field processor (75) and similarly exhibits uninterrupted operation at a constant uniform data rate. A video recorder/playback device (85) receives a constant uniform data rate datastream from an interface/buffer (84) after removal of overhead information, and outputs a constant uniform data rate datastream to the transport decoder.