公开(公告)号：US20070113018A1

公开(公告)日：2007-05-17

申请号：US11273809

申请日：2005-11-14

申请人： Peter Brink ,  Shrikant Shah ,  Peter Munguia

发明人： Peter Brink ,  Shrikant Shah ,  Peter Munguia

IPC分类号： G06F12/00

CPC分类号： G06F12/0862

摘要： A discussion of a local memory with at least a command block section and a cache section that facilitates an efficient interrupt processing. The command-block section is allocated on a per interrupt basis and contains pointers to cache-lines. When an interrupt is recognized an interrupt, the proposal uses the pointers in the command-block to prefetch the corresponding cache-lines from the cache section of the local memory, which it loads into its local cache buffer. Thus, when the CPU recognizes an interrupt, the information for the context-switch is already available in cache.

摘要翻译： 对至少具有命令块部分和缓存部分的本地存储器的讨论有助于有效的中断处理。 命令块部分以每个中断为基础分配，并包含指向高速缓存行的指针。 当中断被识别为中断时，提案使用命令块中的指针从本地存储器的高速缓存部分预取相应的高速缓存行，并将其加载到其本地缓存缓冲区中。 因此，当CPU识别到中断时，上下文切换的信息已经在高速缓存中可用。

公开(公告)号：US20070005858A1

公开(公告)日：2007-01-04

申请号：US11171862

申请日：2005-06-30

申请人： Shrikant Shah ,  Peter Brink ,  Peter Munguia

发明人： Shrikant Shah ,  Peter Brink ,  Peter Munguia

IPC分类号： G06F12/14

CPC分类号： G06F13/24

摘要： Methods and arrangements to extend message signal interrupt (MSI) transactions with additional data to reduce the latency associated with servicing interrupts included in the transactions are contemplated. Some embodiments may comprise a chipset that transmits the MSI to a processor to service the interrupt. The chipset may identify that a transaction is an extended MSI transaction by determining that the MSI has more than a four bytes. In several embodiments, the chipset may validate the MSI by determining that the MSI comprises at least six bytes and, in further embodiments, by determining that the extended MSI has a valid signature byte. Another embodiment comprises a processor to receive the extended MSI transaction and store the data to service the corresponding interrupt(s) in a low latency buffer. The processor may then service the interrupt(s) based upon the data when the processor becomes available.

摘要翻译： 预期用于扩展具有附加数据的消息信号中断（MSI）事务以减少与事务中包括的服务中断相关联的延迟的方法和布置。 一些实施例可以包括将MSI发送到处理器来服务于中断的芯片组。 芯片组可以通过确定MSI具有多于四个字节来识别事务是扩展的MSI事务。 在几个实施例中，芯片组可以通过确定MSI包括至少六个字节并且在另外的实施例中通过确定扩展MSI具有有效的签名字节来验证MSI。 另一个实施例包括处理器，用于接收扩展的MSI事务并存储数据以服务于低延迟缓冲器中的相应中断。 然后，当处理器变得可用时，处理器可以基于数据来服务中断。

公开(公告)号：US20050228917A1

公开(公告)日：2005-10-13

申请号：US10813602

申请日：2004-03-30

申请人： Peter Brink ,  Shrikant Shah

发明人： Peter Brink ,  Shrikant Shah

IPC分类号： G06F12/00 ,  G06F13/24

CPC分类号： G06F13/24

摘要： An electronic system includes a processor and an interrupt structure. The interrupt structure handles interrupt information such as interrupt requests, interrupt function types, and interrupt data without involving the processor. The processor performs interrupt functions according to the interrupt information at times independent from the times the interrupt requests are received by the interrupt structure.

摘要翻译： 电子系统包括处理器和中断结构。 中断结构处理中断请求，中断功能类型和中断数据等中断信息，而不涉及处理器。 处理器根据中断信息执行中断功能，时间独立于中断结构接收到中断请求的时间。

公开(公告)号：US20060004946A1

公开(公告)日：2006-01-05

申请号：US10882073

申请日：2004-06-30

申请人： Shrikant Shah ,  Chetan Rawal

发明人： Shrikant Shah ,  Chetan Rawal

IPC分类号： G06F12/00

CPC分类号： G06F13/28 ,  G06F3/0601 ,  G06F2003/0692

摘要： A method and apparatus for high performance volatile disk drive (VDD) memory access using an integrated direct memory access (DMA) engine. In one embodiment, the method includes the detection of a data access request to VDD memory implemented within volatile system memory. Once a data access request is detected, a VDD driver may issue a DMA data request to perform the data access request from the VDD. Accordingly, in one embodiment, the job of transferring data to/from a VDD memory implemented within an allocated portion of volatile system memory is offloaded to a DMA engine, such as, for example, an integrated DMA engine within a memory controller hub (MCH). Other embodiments are described and claimed.