Intermesh memory device
    2.
    发明授权
    Intermesh memory device 失效
    Intermesh内存设备

    公开(公告)号:US06842369B2

    公开(公告)日:2005-01-11

    申请号:US10141609

    申请日:2002-05-07

    CPC分类号: G11C17/00 G11C5/025

    摘要: An intermesh memory device includes memory components that each have a determinable resistance value and electronic switches that each control current through one or more of the memory components such that a potential is applied to the memory components. A first electronic switch of the intermesh memory device is electrically coupled to an input of a memory component and a second electronic switch is electrically coupled to an output of the memory component. The first electronic switch and the second electronic switch are configured together to apply a potential to the memory component.

    摘要翻译: 互相间存储器件包括每个具有可确定电阻值的存储器组件和每个通过一个或多个存储器组件控制电流的电子开关,使得将电位施加到存储器组件。 互连存储器件的第一电子开关电耦合到存储器组件的输入端,而第二电子开关电耦合到存储器组件的输出端。 第一电子开关和第二电子开关被配置在一起以向存储器组件施加电位。

    Tunnel-junction structures and methods
    3.
    发明授权
    Tunnel-junction structures and methods 失效
    隧道结结构和方法

    公开(公告)号:US06821848B2

    公开(公告)日:2004-11-23

    申请号:US10286157

    申请日:2002-10-30

    IPC分类号: H01L21336

    摘要: Tunnel-junction structures are fabricated by any of a set of related methods that form two or more tunnel junctions simultaneously. The fabrication methods disclosed are compatible with conventional CMOS fabrication practices, including both single damascene and dual damascene processes. The simultaneously formed tunnel junctions may have different areas. In some embodiments, tub-well structures are formed with sloped sidewalls. In some embodiments, an oxide-metal-oxide film stack on the sidewall of a tub-well is etched to form the tunnel junctions. Memory circuits, other integrated circuit structures, substrates carrying microelectronics, and other electronic devices made by the methods are disclosed.

    摘要翻译: 隧道结结构通过同时形成两个或更多个隧道结的一组相关方法中的任一种来制造。 所公开的制造方法与常规CMOS制造实践兼容,包括单镶嵌和双镶嵌工艺。 同时形成的隧道结可以具有不同的区域。 在一些实施例中,浴盆结构形成有倾斜的侧壁。 在一些实施例中,蚀刻在浴缸的侧壁上的氧化物 - 金属氧化物膜堆叠以形成隧道结。 公开了存储电路,其它集成电路结构,携带微电子的衬底以及通过该方法制造的其它电子器件。

    Cubic memory array with diagonal select lines
    6.
    发明授权
    Cubic memory array with diagonal select lines 失效
    具有对角选择线的立方体存储器阵列

    公开(公告)号:US06687147B2

    公开(公告)日:2004-02-03

    申请号:US10202174

    申请日:2002-07-23

    IPC分类号: G11C506

    摘要: A method of creating a memory circuit preferably includes (1) forming a first plurality of select-lines in a plane substantially parallel to a substrate, (2) forming a second plurality of select-lines in a plane substantially parallel to the substrate, where the second plurality of select-lines is divided into first and second groups, where the first group is formed in a direction normal to that of the first plurality of select-lines and the second group is formed in a direction substantially diagonal to that of the first group, (3) forming a plurality of pillars normal to the substrate, and (4) forming an array of memory cells, each memory cell being respectively coupled to a pillar and one of each of said first and second pluralities of select-lines.

    摘要翻译: 一种创建存储器电路的方法优选地包括:(1)在基本上平行于衬底的平面中形成第一组多个选择线,(2)在基本上平行于衬底的平面中形成第二组选择线,其中 第二组选择线被分成第一组和第二组,其中第一组形成在与第一组多个选择线的方向垂直的方向上,并且第二组形成在与第一组大致对角线的方向上 第一组,(3)形成与衬底垂直的多个支柱,以及(4)形成存储器单元的阵列,每个存储单元分别耦合到一个柱和每个所述第一和第二多个选择线中的一个 。

    Interconnection structure and methods
    7.
    发明授权
    Interconnection structure and methods 失效
    互连结构与方法

    公开(公告)号:US06661691B2

    公开(公告)日:2003-12-09

    申请号:US10115763

    申请日:2002-04-02

    IPC分类号: G11C506

    摘要: Interconnection structures for integrated circuits have a first array of cells, at least a second array of cells parallel to the first array, and interconnections disposed for connecting cells of the first array with cells of the second array, at least some of the interconnections being disposed along axes oriented obliquely to the first and second arrays. First and second sets of oblique axes of interconnections may be parallel or opposed to each other. The interconnections may include obliquely slanted pillars or stair-stepped pillars disposed along the oblique axes. Methods for fabricating and using such structures are disclosed.

    摘要翻译: 用于集成电路的互连结构具有第一阵列阵列,平行于第一阵列的至少第二阵列阵列,以及布置用于将第一阵列的单元与第二阵列的单元相连接的互连,至少部分布线被布置 沿着与第一和第二阵列倾斜定向的轴。 互连的第一组和第二组倾斜轴线可以彼此平行或相对。 互连可以包括倾斜的立柱或沿斜轴设置的阶梯式柱。 公开了制造和使用这种结构的方法。

    Mechanism to aid optical beam focusing on optical disc
    9.
    发明授权
    Mechanism to aid optical beam focusing on optical disc 失效
    有助于光束聚焦在光盘上的机制

    公开(公告)号:US07103896B2

    公开(公告)日:2006-09-05

    申请号:US10339705

    申请日:2003-01-08

    IPC分类号: G11B11/00

    CPC分类号: G11B7/0037 G11B23/0021

    摘要: An optical disc of one embodiment of the invention is disclosed that includes a first surface, a second surface, an optically writable label area, and an optically writable data area. The first and the second surfaces are oppositely situated to one another. The label area is on one of the first and the second surfaces. The data area is on one of the first and the second surfaces. The mechanism aids proper focusing of an optical beam of an optical disc device on the optically writable label area and on the optically writable data area.

    摘要翻译: 公开了本发明的一个实施例的光盘,其包括第一表面,第二表面,光学可写标签区域和可光学写入的数据区域。 第一和第二表面彼此相对设置。 标签区域位于第一和第二表面中的一个上。 数据区位于第一和第二表面中的一个上。 该机构有助于将光盘装置的光束适当地对准在光学可写标签区域和光学可写数据区域上。