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公开(公告)号:US20160358927A1
公开(公告)日:2016-12-08
申请号:US15049160
申请日:2016-02-22
申请人: Phil Ouk NAM , Yong Hoon SON , Kyung Hyun KIM , Byeong Ju KIM , Kwang Chul PARK , Yeon Sil SOHN , Jin I LEE , Jong Heun LIM , Won Bong JUNG
发明人: Phil Ouk NAM , Yong Hoon SON , Kyung Hyun KIM , Byeong Ju KIM , Kwang Chul PARK , Yeon Sil SOHN , Jin I LEE , Jong Heun LIM , Won Bong JUNG
IPC分类号: H01L27/115 , H01L21/02
CPC分类号: H01L27/1157 , H01L21/02667 , H01L21/02675 , H01L27/11573 , H01L27/11582
摘要: A memory device, including a first memory region including a first substrate, a plurality of first semiconductor devices on the first substrate, and a first interlayer insulating layer covering the plurality of first semiconductor devices; and a second memory region including a second substrate on the first interlayer insulating layer and a plurality of second semiconductor devices on the second substrate, the second substrate including a first region in a plurality of grooves in the first interlayer insulating layer and a second region including grains extending from the first region, the second region being on an upper surface of the first interlayer insulating layer.
摘要翻译: 一种存储器件,包括第一存储区域,包括第一衬底,第一衬底上的多个第一半导体器件以及覆盖多个第一半导体器件的第一层间绝缘层; 以及第二存储区域,包括在所述第一层间绝缘层上的第二衬底和所述第二衬底上的多个第二半导体器件,所述第二衬底包括在所述第一层间绝缘层中的多个沟槽中的第一区域和包括 晶粒从第一区域延伸,第二区域位于第一层间绝缘层的上表面上。
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公开(公告)号:US20170033119A1
公开(公告)日:2017-02-02
申请号:US15165123
申请日:2016-05-26
申请人: Kwang Chul Park , Jang Gn YUN , Won Bong JUNG
发明人: Kwang Chul Park , Jang Gn YUN , Won Bong JUNG
IPC分类号: H01L27/115
CPC分类号: H01L27/11582 , H01L27/11565 , H01L27/1157
摘要: Semiconductor device are provided including a stacked structure having gate electrodes and interlayer insulating layers alternately stacked on a substrate; channel holes extending perpendicular to the substrate through the stacked structure and including channel regions therein; and horizontal parts at lower portions of the stacked structure and including areas in which the channel regions are horizontally elongated from the channel holes. The horizontal parts surround respective channel holes and are connected to each other between at a least portion of the channel holes.
摘要翻译: 提供半导体器件,其包括层叠结构,其具有交替层叠在基板上的栅电极和层间绝缘层; 通孔穿过层叠结构垂直于衬底延伸并且在其中包括沟道区域; 以及层叠结构的下部的水平部分,并且包括沟道区域从通道孔水平伸长的区域。 水平部分围绕相应的通道孔,并且在通道孔的至少部分之间彼此连接。
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