公开(公告)号：US09997534B2

公开(公告)日：2018-06-12

申请号：US15155732

申请日：2016-05-16

申请人： Yong-Hoon Son ,  Kyung-Hyun Kim ,  Byeong-Ju Kim ,  Phil-Ouk Nam ,  Kwang Chul Park ,  Yeon-Sil Sohn ,  Jin-I Lee ,  Jong-Heun Lim ,  Won-Bong Jung ,  Kohji Kanamori

发明人： Yong-Hoon Son ,  Kyung-Hyun Kim ,  Byeong-Ju Kim ,  Phil-Ouk Nam ,  Kwang Chul Park ,  Yeon-Sil Sohn ,  Jin-I Lee ,  Jong-Heun Lim ,  Won-Bong Jung ,  Kohji Kanamori

IPC分类号： H01L29/792 ,  H01L27/11582 ,  H01L23/528

CPC分类号： H01L27/11582 ,  H01L23/528

摘要： A vertical memory device includes a substrate, a channel on the substrate, extending in a vertical direction with respect to a top surface of the substrate, and including a protrusion at a lower portion of the channel, the protrusion extending in a parallel direction with respect to the top surface of the substrate, a semiconductor pattern connecting the protrusion and the substrate, and gate lines stacked and spaced apart from each other in the vertical direction, the gate lines on the protrusion and the semiconductor pattern and surrounding the channel.

公开(公告)号：US20150249093A1

公开(公告)日：2015-09-03

申请号：US14574456

申请日：2014-12-18

申请人： Jeonggil LEE ,  Yeon-Sil SOHN ,  Woonghee SOHN ,  Kihyun YOON ,  Myoungbum LEE ,  Tai-Soo LIM ,  Yong Chae JUNG

发明人： Jeonggil LEE ,  Yeon-Sil SOHN ,  Woonghee SOHN ,  Kihyun YOON ,  Myoungbum LEE ,  Tai-Soo LIM ,  Yong Chae JUNG

IPC分类号： H01L27/115

CPC分类号： H01L27/11582

摘要： Provided is a semiconductor device, including gate structures on a substrate, the gate structures extending parallel to a first direction and being spaced apart from each other by a separation trench interposed therebetween, each of the gate structures including insulating patterns stacked on the substrate and a gate electrode interposed therebetween; vertical pillars connected to the substrate through the gate structures; an insulating spacer in the separation trench covering a sidewall of each of the gate structures; and a diffusion barrier structure between the gate electrode and the insulating spacer.

摘要翻译： 提供了一种半导体器件，其包括在衬底上的栅极结构，栅极结构平行于第一方向延伸并且通过插入其间的分离沟槽彼此间隔开，每个栅极结构包括堆叠在衬底上的绝缘图案， 栅电极插入其间; 通过栅极结构连接到衬底的垂直柱; 隔离沟槽中的绝缘间隔物覆盖每个栅极结构的侧壁; 以及在栅电极和绝缘间隔物之间​​的扩散阻挡结构。

公开(公告)号：US20170062471A1

公开(公告)日：2017-03-02

申请号：US15249389

申请日：2016-08-27

申请人： Yong-Hoon SON ,  JIN-I LEE ,  Kyunghyun KIM ,  Byeongju KIM ,  Phil Ouk NAM ,  Kwangchul PARK ,  Yeon-Sil SOHN ,  JongHeun LIM ,  Wonbong Jung

发明人： Yong-Hoon SON ,  JIN-I LEE ,  Kyunghyun KIM ,  Byeongju KIM ,  Phil Ouk NAM ,  Kwangchul PARK ,  Yeon-Sil SOHN ,  JongHeun LIM ,  Wonbong Jung

IPC分类号： H01L27/115 ,  H01L29/423 ,  H01L29/40 ,  H01L29/792 ,  H01L29/66

CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L29/408 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/7926

摘要： A semiconductor memory device is disclosed. The device may include a stack including gate electrodes stacked on a substrate in a vertical direction and insulating patterns interposed between the gate electrodes, vertical channels passing through the stack and connected to the substrate, a tunnel insulating layer enclosing each of the vertical channels, charge storing patterns provided between the tunnel insulating layer and the gate electrodes and spaced apart from each other in the vertical direction, blocking insulating patterns provided between the charge storing patterns and the gate electrodes and spaced apart from each other in the vertical direction, and a bit line crossing the stack and connected to the vertical channels. The blocking insulating patterns may have a vertical thickness that is greater than that of the gate electrodes.

摘要翻译： 公开了一种半导体存储器件。 该装置可以包括堆叠，其包括沿垂直方向堆叠在基板上的栅电极和插入在栅电极之间的绝缘图案，穿过堆叠并连接到基板的垂直沟道，围绕每个垂直沟道的隧道绝缘层，电荷 存储设置在隧道绝缘层和栅电极之间并在垂直方向上彼此间隔开的图案，阻止在电荷存储图案和栅电极之间设置并且在垂直方向上彼此间隔开的绝缘图案，以及位 线穿过堆叠并连接到垂直通道。 阻挡绝缘图案可以具有大于栅极电极的垂直厚度。

公开(公告)号：US20120064682A1

公开(公告)日：2012-03-15

申请号：US13230447

申请日：2011-09-12

申请人： Kyung-Tae Jang ,  Myoung Lee ,  Seungmok Shin ,  JinGyun Kim ,  Yeon-Sil Sohn ,  Seung-Yuo Lee ,  Dae-Hun Choi

发明人： Kyung-Tae Jang ,  Myoung Lee ,  Seungmok Shin ,  JinGyun Kim ,  Yeon-Sil Sohn ,  Seung-Yuo Lee ,  Dae-Hun Choi

IPC分类号： H01L21/8239

CPC分类号： H01L21/8239 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/31111 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/40114 ,  H01L29/40117

摘要： Methods of manufacturing a three-dimensional semiconductor device are provided. The method includes: forming a thin film structure, where first and second material layers of at least 2n (n is an integer more than 2) are alternately and repeatedly stacked, on a substrate; wherein the first material layer applies a stress in a range of about 0.1×109 dyne/cm2 to about 10×109 dyne/cm2 to the substrate and the second material layer applies a stress in a range of about −0.1×109 dyne/cm2 to about −10×109 dyne/cm2 to the substrate.

摘要翻译： 提供制造三维半导体器件的方法。 该方法包括：在基板上形成薄膜结构，其中至少2n（n是大于2的整数）的第一和第二材料层交替重复堆叠; 其中所述第一材料层向所述基板施加约0.1×10 9达因/ cm 2至约10×10 9达因/ cm 2的范围内的应力，并且所述第二材料层施加约-0.1×109达因/ cm2的范围内的应力 至约-10×109达因/平方厘米。

公开(公告)号：US20160358927A1

公开(公告)日：2016-12-08

申请号：US15049160

申请日：2016-02-22

申请人： Phil Ouk NAM ,  Yong Hoon SON ,  Kyung Hyun KIM ,  Byeong Ju KIM ,  Kwang Chul PARK ,  Yeon Sil SOHN ,  Jin I LEE ,  Jong Heun LIM ,  Won Bong JUNG

发明人： Phil Ouk NAM ,  Yong Hoon SON ,  Kyung Hyun KIM ,  Byeong Ju KIM ,  Kwang Chul PARK ,  Yeon Sil SOHN ,  Jin I LEE ,  Jong Heun LIM ,  Won Bong JUNG

IPC分类号： H01L27/115 ,  H01L21/02

CPC分类号： H01L27/1157 ,  H01L21/02667 ,  H01L21/02675 ,  H01L27/11573 ,  H01L27/11582

摘要： A memory device, including a first memory region including a first substrate, a plurality of first semiconductor devices on the first substrate, and a first interlayer insulating layer covering the plurality of first semiconductor devices; and a second memory region including a second substrate on the first interlayer insulating layer and a plurality of second semiconductor devices on the second substrate, the second substrate including a first region in a plurality of grooves in the first interlayer insulating layer and a second region including grains extending from the first region, the second region being on an upper surface of the first interlayer insulating layer.

摘要翻译： 一种存储器件，包括第一存储区域，包括第一衬底，第一衬底上的多个第一半导体器件以及覆盖多个第一半导体器件的第一层间绝缘层; 以及第二存储区域，包括在所述第一层间绝缘层上的第二衬底和所述第二衬底上的多个第二半导体器件，所述第二衬底包括在所述第一层间绝缘层中的多个沟槽中的第一区域和包括 晶粒从第一区域延伸，第二区域位于第一层间绝缘层的上表面上。

公开(公告)号：US10559580B2

公开(公告)日：2020-02-11

申请号：US15247602

申请日：2016-08-25

申请人： Yong-Hoon Son ,  Kyunghyun Kim ,  Byeongju Kim ,  Phil Ouk Nam ,  Kwangchul Park ,  Yeon-Sil Sohn ,  Jin-I Lee ,  Wonbong Jung

发明人： Yong-Hoon Son ,  Kyunghyun Kim ,  Byeongju Kim ,  Phil Ouk Nam ,  Kwangchul Park ,  Yeon-Sil Sohn ,  Jin-I Lee ,  Wonbong Jung

IPC分类号： H01L27/11568 ,  H01L27/11565 ,  H01L27/11582 ,  G11C16/04

摘要： A semiconductor memory device includes insulating patterns and gate patterns alternately stacked on a substrate, a channel structure that intersects the insulating patterns and the gate patterns and connected to the substrate, a charge storage structure between the channel structure and the gate patterns, and a contact structure on the substrate at a side of the insulating patterns and the gate patterns. One of the gate patterns includes a first barrier pattern between a first insulating pattern of the insulating patterns and a second insulating pattern of the insulating patterns adjacent the first insulating pattern in a first direction perpendicular to a main surface of the substrate, the first barrier pattern defining a concave region between a first portion of the first barrier pattern extending along the first insulating pattern and a second portion extending along the second insulating pattern, and a metal pattern in the concave region.

公开(公告)号：US10074560B2

公开(公告)日：2018-09-11

申请号：US15601045

申请日：2017-05-22

申请人： Ki-hyun Yoon ,  Hauk Han ,  Yeon-sil Sohn ,  Seul-gi Bae ,  Hyun-seok Lim

发明人： Ki-hyun Yoon ,  Hauk Han ,  Yeon-sil Sohn ,  Seul-gi Bae ,  Hyun-seok Lim

IPC分类号： H01L21/768 ,  H01L21/28 ,  H01L29/40 ,  H01L29/66 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11578 ,  H01L29/792 ,  H01L21/822 ,  H01L27/11568 ,  H01L21/8239 ,  H01L27/105 ,  H01L27/11551

CPC分类号： H01L21/76841 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/76843 ,  H01L21/76858 ,  H01L21/76865 ,  H01L21/8221 ,  H01L21/8239 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53271 ,  H01L27/1052 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/401 ,  H01L29/66477 ,  H01L29/78642 ,  H01L29/792 ,  H01L29/7926

摘要： A method of manufacturing a semiconductor device includes forming an insulating pattern layer on a substrate, conformally forming a first conductive layer with a first thickness on the insulating pattern layer, wet etching the first conductive layer to have a second thickness that is less than the first thickness, and forming a second conductive layer on the first conductive layer after wet etching the first conductive layer. The second conductive layer includes a material that is different from a material included in the first conductive layer.

公开(公告)号：US20180090325A1

公开(公告)日：2018-03-29

申请号：US15601045

申请日：2017-05-22

申请人： Ki-hyun YOON ,  Hauk HAN ,  Yeon-sil SOHN ,  Seul-gi BAE ,  Hyun-seok LIM

发明人： Ki-hyun YOON ,  Hauk HAN ,  Yeon-sil SOHN ,  Seul-gi BAE ,  Hyun-seok LIM

IPC分类号： H01L21/28 ,  H01L29/40 ,  H01L29/66 ,  H01L27/11556 ,  H01L27/11582

CPC分类号： H01L21/76841 ,  H01L21/28088 ,  H01L21/8221 ,  H01L21/8239 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53271 ,  H01L27/1052 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/401 ,  H01L29/66477 ,  H01L29/792 ,  H01L29/7926

摘要： A method of manufacturing a semiconductor device includes forming an insulating pattern layer on a substrate, conformally forming a first conductive layer with a first thickness on the insulating pattern layer, wet etching the first conductive layer to have a second thickness that is less than the first thickness, and forming a second conductive layer on the first conductive layer after wet etching the first conductive layer. The second conductive layer includes a material that is different from a material included in the first conductive layer.

公开(公告)号：US20170098656A1

公开(公告)日：2017-04-06

申请号：US15247602

申请日：2016-08-25

申请人： Yong-Hoon Son ,  Kyunghyun KIM ,  Byeongju KIM ,  Phil Ouk NAM ,  Kwangchul PARK ,  Yeon-Sil SOHN ,  Jin-I LEE ,  Wonbong Jung

发明人： Yong-Hoon Son ,  Kyunghyun KIM ,  Byeongju KIM ,  Phil Ouk NAM ,  Kwangchul PARK ,  Yeon-Sil SOHN ,  Jin-I LEE ,  Wonbong Jung

IPC分类号： H01L27/115 ,  G11C16/04

摘要： A semiconductor memory device includes insulating patterns and gate patterns alternately stacked on a substrate, a channel structure that intersects the insulating patterns and the gate patterns and connected to the substrate, a charge storage structure between the channel structure and the gate patterns, and a contact structure on the substrate at a side of the insulating patterns and the gate patterns. One of the gate patterns includes a first barrier pattern between a first insulating pattern of the insulating patterns and a second insulating pattern of the insulating patterns adjacent the first insulating pattern in a first direction perpendicular to a main surface of the substrate, the first barrier pattern defining a concave region between a first portion of the first barrier pattern extending along the first insulating pattern and a second portion extending along the second insulating pattern, and a metal pattern in the concave region.

公开(公告)号：US20170069637A1

公开(公告)日：2017-03-09

申请号：US15251580

申请日：2016-08-30

申请人： YONG-HOON SON ,  JONG-WON KIM ,  CHANG-SEOK KANG ,  YOUNG-WOO PARK ,  JAE-DUK LEE ,  KYUNG-HYUN KIM ,  BYEONG-JU KIM ,  PHIL-OUK NAM ,  KWANG-CHUL PARK ,  YEON-SIL SOHN ,  JIN-I LEE ,  WON-BONG JUNG

发明人： YONG-HOON SON ,  JONG-WON KIM ,  CHANG-SEOK KANG ,  YOUNG-WOO PARK ,  JAE-DUK LEE ,  KYUNG-HYUN KIM ,  BYEONG-JU KIM ,  PHIL-OUK NAM ,  KWANG-CHUL PARK ,  YEON-SIL SOHN ,  JIN-I LEE ,  WON-BONG JUNG

IPC分类号： H01L27/115 ,  H01L29/66

CPC分类号： H01L27/1157 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/66833

摘要： A nonvolatile memory device includes a conductive line disposed on a substrate and vertically extended from the substrate, a first channel layer disposed on the substrate and vertically extended from the substrate, wherein the first channel layer is spaced apart from the conductive line, a second channel layer vertically extended from the substrate, wherein the second channel layer is disposed between the first channel layer and the conductive line, a first gate electrode disposed between the conductive line and the second channel layer, wherein the first gate electrode includes a first portion having a first thickness and a second portion having a second thickness that is different from the first thickness, and a second gate electrode disposed between the first channel layer and the second channel layer, wherein the second gate electrode has the second thickness.

摘要翻译： 非易失性存储器件包括设置在衬底上并从衬底垂直延伸的导线，设置在衬底上并从衬底垂直延伸的第一沟道层，其中第一沟道层与导电线间隔开，第二沟道 层，其中所述第二沟道层设置在所述第一沟道层和所述导电线之间;第一栅极，设置在所述导电线和所述第二沟道层之间，其中所述第一栅电极包括第一部分，所述第一部分具有 第一厚度和具有不同于第一厚度的第二厚度的第二部分，以及设置在第一沟道层和第二沟道层之间的第二栅电极，其中第二栅电极具有第二厚度。