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    VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME
    3.
    发明申请
    VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
    垂直存储器件及其制造方法

    公开(公告)号：US20150145021A1

    公开(公告)日：2015-05-28

    申请号：US14517025

    申请日：2014-10-17

    申请人： Byong-Hyun Jang ,  Dong-Chul Yoo ,  Ki-Hyun Hwang ,  Phil-Ouk Nam ,  Jae-Young Ahn

    发明人： Byong-Hyun Jang ,  Dong-Chul Yoo ,  Ki-Hyun Hwang ,  Phil-Ouk Nam ,  Jae-Young Ahn

    IPC分类号： H01L27/115 ,  H01L29/51

    CPC分类号： H01L27/11565 ,  H01L27/1158 ,  H01L29/66833 ,  H01L29/7926

    摘要： Nonvolatile memory devices include at least four cylindrical-shaped channel regions, which extend vertically from portions of a substrate located at respective vertices of at least one rhomboid when viewed in a vertical direction relative to a surface of the substrate. A charge storage layer (e.g., ONO layer) is provided on an outer sidewall of each of the cylindrical-shaped channel regions. In addition, to achieve a high degree of integration, a plurality of vertically-stacked gate electrodes are provided, which extend adjacent each of the cylindrical-shaped channel regions.

    摘要翻译： 非易失性存储器件包括至少四个圆柱形沟道区域，当从垂直于衬底表面的垂直方向观察时，至少四个圆柱形沟道区域从位于至少一个菱形晶体的相应顶点处的衬底的部分垂直延伸。 电荷存储层（例如，ONO层）设置在每个圆柱形沟道区的外侧壁上。 此外，为了实现高度的集成，提供了多个垂直堆叠的栅电极，其在每个圆柱形沟道区域附近延伸。

    Vertical structure non-volatile memory device and method of manufacturing the same
    4.
    发明授权
    Vertical structure non-volatile memory device and method of manufacturing the same 有权
    垂直结构非易失性存储器件及其制造方法

    公开(公告)号：US08748249B2

    公开(公告)日：2014-06-10

    申请号：US13456415

    申请日：2012-04-26

    申请人： Jun-kyu Yang ,  Ki-hyun Hwang ,  Phil-ouk Nam ,  Jae-young Ahn ,  Han-mei Choi ,  Dong-chul Yoo

    发明人： Jun-kyu Yang ,  Ki-hyun Hwang ,  Phil-ouk Nam ,  Jae-young Ahn ,  Han-mei Choi ,  Dong-chul Yoo

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/7926 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/7889

    摘要： A vertical structure non-volatile memory device in which a gate dielectric layer is prevented from protruding toward a substrate; a resistance of a ground selection line (GSL) electrode is reduced so that the non-volatile memory device is highly integrated and has improved reliability, and a method of manufacturing the same are provided. The method includes: sequentially forming a polysilicon layer and an insulating layer on a silicon substrate; forming a gate dielectric layer and a channel layer through the polysilicon layer and the insulating layer, the gate dielectric layer and the channel layer extending in a direction perpendicular to the silicon substrate; forming an opening for exposing the silicon substrate, through the insulating layer and the polysilicon layer; removing the polysilicon layer exposed through the opening, by using a halogen-containing reaction gas at a predetermined temperature; and filling a metallic layer in the space formed by removing the polysilicon layer.

    摘要翻译： 一种垂直结构的非易失性存储器件，其中防止栅介质层向衬底突出; 降低了接地选择线（GSL）电极的电阻，使得非易失性存储器件高度集成并且具有改进的可靠性，并且提供了其制造方法。 该方法包括：在硅衬底上依次形成多晶硅层和绝缘层; 通过所述多晶硅层和所述绝缘层形成栅介质层和沟道层，所述栅介质层和所述沟道层在垂直于所述硅衬底的方向上延伸; 形成用于使所述硅衬底暴露于所述绝缘层和所述多晶硅层的开口; 通过在预定温度下使用含卤素反应气体去除通过开口暴露的多晶硅层; 并在通过去除多晶硅层形成的空间中填充金属层。

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS FOR MANUFACTURING SAME
    5.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS FOR MANUFACTURING SAME 有权
    三维半导体存储器件及其制造方法

    公开(公告)号：US20130313631A1

    公开(公告)日：2013-11-28

    申请号：US13828557

    申请日：2013-03-14

    申请人： Junkyu Yang ,  Phil Ouk Nam ,  Youngseon Son ,  Kwangyoung Lee ,  Kihyun Hwang

    发明人： Junkyu Yang ,  Phil Ouk Nam ,  Youngseon Son ,  Kwangyoung Lee ,  Kihyun Hwang

    IPC分类号： H01L27/088

    CPC分类号： H01L27/088 ,  H01L27/11556 ,  H01L27/11578

    摘要： A three-dimensional (3D) nonvolatile memory device includes a vertical stack of nonvolatile memory cells on a substrate having a region of first conductivity type therein. A dopant region of second conductivity type is provided in the substrate. This dopant region forms a P—N rectifying junction with the region of first conductivity type and has a concave upper surface that is recessed relative to an upper surface of the substrate upon which the vertical stack of nonvolatile memory cells extends. An electrically insulating electrode separating pattern is provided, which extends through the vertical stack of nonvolatile memory cells and into the recess in the dopant region of second conductivity type.

    摘要翻译： 三维（3D）非易失性存储器件包括在其中具有第一导电类型区域的衬底上的非易失性存储器单元的垂直堆叠。 在基板中设置第二导电类型的掺杂区域。 该掺杂剂区域与第一导电类型的区域形成P-N整流结，并且具有相对于垂直堆叠的非易失性存储单元延伸的衬底的上表面凹陷的凹上表面。 提供电绝缘电极分离图案，其延伸穿过垂直堆叠的非易失性存储单元并进入第二导电类型的掺杂区域中的凹槽中。

    Semiconductor Memory Devices
    9.
    发明申请
    Semiconductor Memory Devices 审中-公开

    公开(公告)号：US20170098656A1

    公开(公告)日：2017-04-06

    申请号：US15247602

    申请日：2016-08-25

    申请人： Yong-Hoon Son ,  Kyunghyun KIM ,  Byeongju KIM ,  Phil Ouk NAM ,  Kwangchul PARK ,  Yeon-Sil SOHN ,  Jin-I LEE ,  Wonbong Jung

    发明人： Yong-Hoon Son ,  Kyunghyun KIM ,  Byeongju KIM ,  Phil Ouk NAM ,  Kwangchul PARK ,  Yeon-Sil SOHN ,  Jin-I LEE ,  Wonbong Jung

    IPC分类号： H01L27/115 ,  G11C16/04

    摘要： A semiconductor memory device includes insulating patterns and gate patterns alternately stacked on a substrate, a channel structure that intersects the insulating patterns and the gate patterns and connected to the substrate, a charge storage structure between the channel structure and the gate patterns, and a contact structure on the substrate at a side of the insulating patterns and the gate patterns. One of the gate patterns includes a first barrier pattern between a first insulating pattern of the insulating patterns and a second insulating pattern of the insulating patterns adjacent the first insulating pattern in a first direction perpendicular to a main surface of the substrate, the first barrier pattern defining a concave region between a first portion of the first barrier pattern extending along the first insulating pattern and a second portion extending along the second insulating pattern, and a metal pattern in the concave region.