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1.发明授权System and method for adaptively deskewing parallel data signals relative to a clock 有权用于相对于时钟自适应地偏移并行数据信号的系统和方法公开(公告)号：US08031823B2
公开(公告)日：2011-10-04
申请号：US12247122
申请日：2008-10-07
IPC分类号： H04L7/00
CPC分类号： G06F1/10 , H04L7/0041 , H04L7/02
摘要： A system and method of reducing skew between a plurality of signals transmitted with a transmit clock is described. Skew is detected between the received transmit clock and each of received data signals. Delay is added to the clock or to one or more of the plurality of data signals to compensate for the detected skew. The delay added to each of the plurality of delayed signals is updated to adapt to changes in detected skew.
摘要翻译： 描述了减少用传输时钟发送的多个信号之间的偏差的系统和方法。 在所接收的发送时钟和接收到的每个数据信号之间检测到偏斜。 延迟被添加到时钟或多个数据信号中的一个或多个以补偿检测到的偏斜。 增加到多个延迟信号中的每一个的延迟被更新以适应检测到的偏斜的变化。
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2.发明申请SYSTEM AND METHOD FOR ADAPTIVELY DESKEWING PARALLEL DATA SIGNALS RELATIVE TO A CLOCK 有权与时钟相关的适应性平行数据信号的系统和方法公开(公告)号：US20090034673A1
公开(公告)日：2009-02-05
申请号：US12247122
申请日：2008-10-07
CPC分类号： G06F1/10 , H04L7/0041 , H04L7/02
摘要： A system and method of reducing skew between a plurality of signals transmitted with a transmit clock is described. Skew is detected between the received transmit clock and each of received data signals. Delay is added to the clock or to one or more of the plurality of data signals to compensate for the detected skew. The delay added to each of the plurality of delayed signals is updated to adapt to changes in detected skew.
摘要翻译： 描述了减少用传输时钟发送的多个信号之间的偏差的系统和方法。 在所接收的发送时钟和接收到的每个数据信号之间检测到偏斜。 延迟被添加到时钟或多个数据信号中的一个或多个以补偿检测到的偏斜。 增加到多个延迟信号中的每一个的延迟被更新以适应检测到的偏斜的变化。
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3.发明授权System and method for adaptively deskewing parallel data signals relative to a clock 有权用于相对于时钟自适应地偏移并行数据信号的系统和方法公开(公告)号：US07433441B2
公开(公告)日：2008-10-07
申请号：US11405387
申请日：2006-04-17
IPC分类号： H04L7/00
CPC分类号： G06F1/10 , H04L7/0041 , H04L7/02
摘要： A system and method of reducing skew between a plurality of signals transmitted with a transmit clock is described. Skew is detected between the received transmit clock and each of received data signals. Delay is added to the clock or to one or more of the plurality of data signals to compensate for the detected skew. The delay added to each of the plurality of delayed signals is updated to adapt to changes in detected skew.
摘要翻译： 描述了减少用传输时钟发送的多个信号之间的偏差的系统和方法。 在所接收的发送时钟和接收到的每个数据信号之间检测到偏斜。 延迟被添加到时钟或多个数据信号中的一个或多个以补偿检测到的偏斜。 增加到多个延迟信号中的每一个的延迟被更新以适应检测到的偏斜的变化。
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4.发明授权System and method for adaptively deskewing parallel data signals relative to a clock 有权用于相对于时钟自适应地偏移并行数据信号的系统和方法公开(公告)号：US07031420B1
公开(公告)日：2006-04-18
申请号：US09476678
申请日：1999-12-30
IPC分类号： H04L25/00
CPC分类号： G06F1/10 , H04L7/0041 , H04L7/02
摘要： A system and method of reducing skew between a plurality of signals transmitted with a transmit clock is described. Skew is detected between the received transmit clock and each of received data signals. Delay is added to the clock or to one or more of the plurality of data signals to compensate for the detected skew. Each of the plurality of delayed signals is compared to a reference signal to detect changes in the skew. The delay added to each of the plurality of delayed signals is updated to adapt to changes in the detected skew.
摘要翻译： 描述了减少用传输时钟发送的多个信号之间的偏差的系统和方法。 在所接收的发送时钟和接收到的每个数据信号之间检测到偏斜。 延迟被添加到时钟或多个数据信号中的一个或多个以补偿检测到的偏斜。 将多个延迟信号中的每一个与参考信号进行比较，以检测偏斜的变化。 增加到多个延迟信号中的每一个的延迟被更新以适应检测到的偏斜的变化。
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公开(公告)号：US06803872B2
公开(公告)日：2004-10-12
申请号：US10143413
申请日：2002-05-09
IPC分类号： H03M136
CPC分类号： H03K5/135 , H03K2005/00208
摘要： Circuitry that provides additional delay to early arriving signals such that all data signals arrive at a receiving latch with same path delay. The delay of a forwarded clock reference is also controlled such that the capturing clock edge will be optimally positioned near quadrature (depending on latch setup/hold requirements). The circuitry continuously adapts to data and clock path delay changes and digital filtering of phase measurements reduce errors brought on by jittering data edges. The circuitry utilizes only the minimum amount of delay necessary to achieve objective thereby limiting any unintended jitter. Particularly, this programmable differential delay circuit with fine delay adjustment is designed to allow the skew between ASICS to be minimized. This includes skew between data bits, between data bits and clocks as well as minimizing the overall skew in a channel between ASICS.
摘要翻译： 对早期到达信号提供附加延迟的电路，使得所有数据信号到达具有相同路径延迟的接收锁存器。 还控制转发的时钟参考的延迟，使得捕获时钟边缘将被最佳地定位在正交附近（取决于锁存器设置/保持要求）。 该电路连续适应数据和时钟路径延迟变化，并且相位测量的数字滤波可以减少抖动数据沿引起的误差。 电路仅利用实现目标所需的最小延迟量，从而限制任何非预期的抖动。 特别地，具有精细延迟调整的可编程差分延迟电路被设计为允许ASICS之间的偏斜最小化。 这包括数据位之间，数据位和时钟之间的偏差以及最小化ASICS之间通道中的总体偏移。
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公开(公告)号：US06486723B1
公开(公告)日：2002-11-26
申请号：US10142472
申请日：2002-05-09
IPC分类号： H03H1126
CPC分类号： H03K5/135 , H03K2005/00208
摘要： Circuitry that provides additional delay to early arriving signals such that all data signals arrive at a receiving latch with same path delay. The delay of a forwarded clock reference is also controlled such that the capturing clock edge will be optimally positioned near quadrature (depending on latch setup/hold requirements). The circuitry continuously adapts to data and clock path delay changes and digital filtering of phase measurements reduce errors brought on by jittering data edges. The circuitry utilizes only the minimum amount of delay necessary to achieve objective thereby limiting any unintended jitter. Particularly, this programmable differential delay circuit with fine delay adjustment is designed to allow the skew between ASICS to be minimized. This includes skew between data bits, between data bits and clocks as well as minimizing the overall skew in a channel between ASICS.
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公开(公告)号：US06417713B1
公开(公告)日：2002-07-09
申请号：US09475466
申请日：1999-12-30
IPC分类号： H03H1126
CPC分类号： H03K5/135 , H03K2005/00208
摘要： Circuitry that provides additional delay to early arriving signals such that all data signals arrive at a receiving latch with same path delay. The delay of a forwarded clock reference is also controlled such that the capturing clock edge will be optimally positioned near quadrature (depending on latch setup/hold requirements). The circuitry continuously adapts to data and clock path delay changes and digital filtering of phase measurements reduce errors brought on by jittering data edges. The circuitry utilizes only the minimum amount of delay necessary to achieve objective thereby limiting any unintended jitter. Particularly, this programmable differential delay circuit with fine delay adjustment is designed to allow the skew between ASICS to be minimized. This includes skew between data bits, between data bits and clocks as well as minimizing the overall skew in a channel between ASICS.
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