公开(公告)号：US20160056114A1

公开(公告)日：2016-02-25

申请号：US14463982

申请日：2014-08-20

申请人： Zihao M. Gao ,  David C. Burdeaux ,  Wayne R. Burger ,  Robert A. Pryor ,  Philippe Renaud

发明人： Zihao M. Gao ,  David C. Burdeaux ,  Wayne R. Burger ,  Robert A. Pryor ,  Philippe Renaud

IPC分类号： H01L23/60 ,  H01L29/66 ,  H01L29/06 ,  H01L29/40 ,  H01L21/306 ,  H01L21/71 ,  H01L21/265 ,  H01L29/10 ,  H01L29/78 ,  H01L21/283

CPC分类号： H01L23/60 ,  H01L21/26586 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/71 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7817 ,  H01L29/7823 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： A device includes a semiconductor substrate having a surface with a trench, first and second conduction terminals supported by the semiconductor substrate, a control electrode supported by the semiconductor substrate between the first and second conduction terminals and configured to control flow of charge carriers during operation between the first and second conduction terminals, and a Faraday shield supported by the semiconductor substrate and disposed between the control electrode and the second conduction terminal. At least a portion of the Faraday shield is disposed in the trench.

摘要翻译： 一种器件包括具有沟槽的表面的半导体衬底，由半导体衬底支撑的第一和第二导电端子，由第一和第二导电端子之间的半导体衬底支撑的控制电极，并且被配置为在第一和第二导电端子之间的运行期间控制电荷载流子的流动 第一和第二导电端子以及由半导体衬底支撑并设置在控制电极和第二导电端子之间的法拉第屏蔽。 法拉第屏蔽的至少一部分设置在沟槽中。

公开(公告)号：US20160035822A1

公开(公告)日：2016-02-04

申请号：US14447157

申请日：2014-07-30

申请人： Philippe Renaud ,  Zihao M. Gao

发明人： Philippe Renaud ,  Zihao M. Gao

IPC分类号： H01L29/06 ,  H01L21/266 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10

CPC分类号： H01L29/7835 ,  H01L21/26513 ,  H01L21/266 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/66575 ,  H01L29/66659

摘要： Semiconductor devices include: (a) a semiconductor substrate containing a source region and a drain region; (b) a gate structure supported by the semiconductor substrate between the source region and the drain region; (c) a composite drift region in the semiconductor substrate, the composite drift region extending laterally from the drain region to at least an edge of the gate structure, the composite drift region including dopant having a first conductivity type, wherein at least a portion of the dopant is buried beneath the drain region at a depth exceeding an ion implantation range; and (d) a well region in the semiconductor substrate, wherein the well region has a second conductivity type and wherein the well region is configured to form a channel therein under the gate structure during operation of the semiconductor device. Methods for the fabrication of semiconductor devices are described.

摘要翻译： 半导体器件包括：（a）含有源极区和漏极区的半导体衬底; （b）在源极区域和漏极区域之间由半导体衬底支撑的栅极结构; （c）所述半导体衬底中的复合漂移区，所述复合漂移区从所述漏极区域横向延伸到所述栅极结构的至少一个边缘，所述复合漂移区域包括具有第一导电类型的掺杂剂，其中至少一部分 掺杂剂以超过离子注入范围的深度埋在漏极区之下; 和（d）半导体衬底中的阱区，其中所述阱区具有第二导电类型，并且其中所述阱区被配置为在所述半导体器件的操作期间在所述栅极结构下方形成沟道。 描述了制造半导体器件的方法。

公开(公告)号：US09520367B2

公开(公告)日：2016-12-13

申请号：US14463982

申请日：2014-08-20

申请人： Zihao M. Gao ,  David C. Burdeaux ,  Wayne R. Burger ,  Robert A. Pryor ,  Philippe Renaud

发明人： Zihao M. Gao ,  David C. Burdeaux ,  Wayne R. Burger ,  Robert A. Pryor ,  Philippe Renaud

IPC分类号： H01L23/60 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/283 ,  H01L21/306 ,  H01L21/71 ,  H01L29/40 ,  H01L29/417 ,  H01L29/08 ,  H01L21/265 ,  H01L29/10

CPC分类号： H01L23/60 ,  H01L21/26586 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/71 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7817 ,  H01L29/7823 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： A device includes a semiconductor substrate having a surface with a trench, first and second conduction terminals supported by the semiconductor substrate, a control electrode supported by the semiconductor substrate between the first and second conduction terminals and configured to control flow of charge carriers during operation between the first and second conduction terminals, and a Faraday shield supported by the semiconductor substrate and disposed between the control electrode and the second conduction terminal. At least a portion of the Faraday shield is disposed in the trench.

摘要翻译： 一种器件包括具有沟槽的表面的半导体衬底，由半导体衬底支撑的第一和第二导电端子，由第一和第二导电端子之间的半导体衬底支撑的控制电极，并且被配置为在第一和第二导电端子之间的运行期间控制电荷载流子的流动 第一和第二导电端子以及由半导体衬底支撑并设置在控制电极和第二导电端子之间的法拉第屏蔽。 法拉第屏蔽的至少一部分设置在沟槽中。

公开(公告)号：US20160181378A1

公开(公告)日：2016-06-23

申请号：US14572773

申请日：2014-12-17

申请人： Zihao M. Gao ,  David C. Burdeaux ,  Agni Mitra

发明人： Zihao M. Gao ,  David C. Burdeaux ,  Agni Mitra

IPC分类号： H01L29/40 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/7823 ,  H01L29/0611 ,  H01L29/0882 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/402 ,  H01L29/404 ,  H01L29/4175 ,  H01L29/66659 ,  H01L29/66712 ,  H01L29/7835

摘要： A transistor includes a surface region, a gate, a source dopant region, a drain dopant region, a drift dopant region, a set of electrically conductive shield plates, and a shield plate dopant region. A sidewall of the gate aligns with a drain side boundary of the surface region. The drain dopant region is within the surface region on the drain side. The drift dopant region is within the surface region between the drain side boundary and the drain dopant region. The set of electrically conductive shield plates includes a first shield plate overlying the drift dopant region. The shield plate dopant region is within the drift dopant region and underlies the set of shield plates.

摘要翻译： 晶体管包括表面区域，栅极，源极掺杂区域，漏极掺杂区域，漂移掺杂区域，一组导电屏蔽板以及屏蔽板掺杂区域。 栅极的侧壁与表面区域的漏极边界对准。 漏极掺杂剂区域在漏极侧的表面区域内。 漂移掺杂剂区域在漏极侧边界和漏极掺杂剂区域之间的表面区域内。 该组导电屏蔽板包括覆盖漂移掺杂剂区域的第一屏蔽板。 屏蔽板掺杂剂区域在漂移掺杂区域内并且位于该组屏蔽板之下。

公开(公告)号：US09437693B2

公开(公告)日：2016-09-06

申请号：US14572773

申请日：2014-12-17

申请人： Zihao M. Gao ,  David C. Burdeaux ,  Agni Mitra

发明人： Zihao M. Gao ,  David C. Burdeaux ,  Agni Mitra

IPC分类号： H01L29/76 ,  H01L29/40 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7823 ,  H01L29/0611 ,  H01L29/0882 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/402 ,  H01L29/404 ,  H01L29/4175 ,  H01L29/66659 ,  H01L29/66712 ,  H01L29/7835

摘要： A transistor includes a surface region, a gate, a source dopant region, a drain dopant region, a drift dopant region, a set of electrically conductive shield plates, and a shield plate dopant region. A sidewall of the gate aligns with a drain side boundary of the surface region. The drain dopant region is within the surface region on the drain side. The drift dopant region is within the surface region between the drain side boundary and the drain dopant region. The set of electrically conductive shield plates includes a first shield plate overlying the drift dopant region. The shield plate dopant region is within the drift dopant region and underlies the set of shield plates.

摘要翻译： 晶体管包括表面区域，栅极，源极掺杂区域，漏极掺杂剂区域，漂移掺杂区域，一组导电屏蔽板以及屏蔽板掺杂区域。 栅极的侧壁与表面区域的漏极边界对准。 漏极掺杂剂区域在漏极侧的表面区域内。 漂移掺杂剂区域在漏极侧边界和漏极掺杂剂区域之间的表面区域内。 该组导电屏蔽板包括覆盖漂移掺杂剂区域的第一屏蔽板。 屏蔽板掺杂剂区域在漂移掺杂区域内并且位于该组屏蔽板之下。