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公开(公告)号：US20160056114A1
公开(公告)日：2016-02-25
申请号：US14463982
申请日：2014-08-20
IPC分类号： H01L23/60 , H01L29/66 , H01L29/06 , H01L29/40 , H01L21/306 , H01L21/71 , H01L21/265 , H01L29/10 , H01L29/78 , H01L21/283
CPC分类号： H01L23/60 , H01L21/26586 , H01L21/283 , H01L21/30604 , H01L21/71 , H01L29/0634 , H01L29/0653 , H01L29/0696 , H01L29/0847 , H01L29/1045 , H01L29/1095 , H01L29/402 , H01L29/404 , H01L29/407 , H01L29/4175 , H01L29/66659 , H01L29/66681 , H01L29/7817 , H01L29/7823 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： A device includes a semiconductor substrate having a surface with a trench, first and second conduction terminals supported by the semiconductor substrate, a control electrode supported by the semiconductor substrate between the first and second conduction terminals and configured to control flow of charge carriers during operation between the first and second conduction terminals, and a Faraday shield supported by the semiconductor substrate and disposed between the control electrode and the second conduction terminal. At least a portion of the Faraday shield is disposed in the trench.
摘要翻译： 一种器件包括具有沟槽的表面的半导体衬底，由半导体衬底支撑的第一和第二导电端子，由第一和第二导电端子之间的半导体衬底支撑的控制电极，并且被配置为在第一和第二导电端子之间的运行期间控制电荷载流子的流动 第一和第二导电端子以及由半导体衬底支撑并设置在控制电极和第二导电端子之间的法拉第屏蔽。 法拉第屏蔽的至少一部分设置在沟槽中。
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公开(公告)号：US08537512B2
公开(公告)日：2013-09-17
申请号：US12393166
申请日：2009-02-26
IPC分类号： H02H9/00
CPC分类号： H01L27/0255 , H01L29/0692 , H01L29/16 , H01L29/861
摘要： An electrostatic discharge (ESD) protection circuit (40) is coupled across input-output (I/O) pads (21) and common terminals (24) of a core circuit (22) to protect it from ESD events. The circuit (40) comprises, a unidirectional ESD clamp (23) and two or more floating diodes (42, 44) arranged in parallel opposed configuration in series with the ESD clamp (23), the combination coupled between the I/O pads (21) and the reference terminals (24). In a preferred arrangement, the two strings of opposed parallel coupled diodes (42, 44) are used with different numbers of diodes in each string. These diodes (42, 44) operate in forward conduction (43, 45), so the energy dissipated therein during an ESD event is much reduced compared to a reverse biased diode and they can have smaller area. Signal clipping at the I/O pad (21) is reduced, less power is dissipated and less chip area is utilized.
摘要翻译： 静电放电（ESD）保护电路（40）耦合在核心电路（22）的输入输出（I / O）焊盘（21）和公共端子（24）之间，以防止ESD事件。 电路（40）包括单向ESD钳位（23）和与ESD钳位（23）串联布置成平行相对构造的两个或更多个浮动二极管（42,44），该组合耦合在I / O焊盘 21）和参考端子（24）。 在优选的布置中，两串相对的并联耦合二极管（42,44）与每个串中使用不同数量的二极管。 这些二极管（42,44）在正向导通（43,45）中工作，因此与反向偏置二极管相比，在ESD事件期间消耗的能量大大降低，并且它们可以具有较小的面积。 I / O焊盘（21）上的信号削波减少，功率消耗减少，芯片面积减少。
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公开(公告)号：US09520367B2
公开(公告)日：2016-12-13
申请号：US14463982
申请日：2014-08-20
IPC分类号： H01L23/60 , H01L29/78 , H01L29/66 , H01L29/06 , H01L21/283 , H01L21/306 , H01L21/71 , H01L29/40 , H01L29/417 , H01L29/08 , H01L21/265 , H01L29/10
CPC分类号： H01L23/60 , H01L21/26586 , H01L21/283 , H01L21/30604 , H01L21/71 , H01L29/0634 , H01L29/0653 , H01L29/0696 , H01L29/0847 , H01L29/1045 , H01L29/1095 , H01L29/402 , H01L29/404 , H01L29/407 , H01L29/4175 , H01L29/66659 , H01L29/66681 , H01L29/7817 , H01L29/7823 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： A device includes a semiconductor substrate having a surface with a trench, first and second conduction terminals supported by the semiconductor substrate, a control electrode supported by the semiconductor substrate between the first and second conduction terminals and configured to control flow of charge carriers during operation between the first and second conduction terminals, and a Faraday shield supported by the semiconductor substrate and disposed between the control electrode and the second conduction terminal. At least a portion of the Faraday shield is disposed in the trench.
摘要翻译： 一种器件包括具有沟槽的表面的半导体衬底，由半导体衬底支撑的第一和第二导电端子，由第一和第二导电端子之间的半导体衬底支撑的控制电极，并且被配置为在第一和第二导电端子之间的运行期间控制电荷载流子的流动 第一和第二导电端子以及由半导体衬底支撑并设置在控制电极和第二导电端子之间的法拉第屏蔽。 法拉第屏蔽的至少一部分设置在沟槽中。
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公开(公告)号：US20100214704A1
公开(公告)日：2010-08-26
申请号：US12393166
申请日：2009-02-26
CPC分类号： H01L27/0255 , H01L29/0692 , H01L29/16 , H01L29/861
摘要： An electrostatic discharge (ESD) protection circuit (40) is coupled across input-output (I/O) pads (21) and common terminals (24) of a core circuit (22) to protect it from ESD events. The circuit (40) comprises, a unidirectional ESD clamp (23) and two or more floating diodes (42, 44) arranged in parallel opposed configuration in series with the ESD clamp (23), the combination coupled between the I/O pads (21) and the reference terminals (24). In a preferred arrangement, the two strings of opposed parallel coupled diodes (42, 44) are used with different numbers of diodes in each string. These diodes (42, 44) operate in forward conduction (43, 45), so the energy dissipated therein during an ESD event is much reduced compared to a reverse biased diode and they can have smaller area. Signal clipping at the I/O pad (21) is reduced, less power is dissipated and less chip area is utilized.
摘要翻译： 静电放电（ESD）保护电路（40）耦合在核心电路（22）的输入输出（I / O）焊盘（21）和公共端子（24）之间，以防止ESD事件。 电路（40）包括单向ESD钳位（23）和与ESD钳位（23）串联布置成平行相对构造的两个或更多个浮动二极管（42,44），该组合耦合在I / O焊盘 21）和参考端子（24）。 在优选的布置中，两串相对的并联耦合二极管（42,44）与每个串中使用不同数量的二极管。 这些二极管（42,44）在正向导通（43,45）中工作，因此与反向偏置二极管相比，在ESD事件期间消耗的能量大大降低，并且它们可以具有较小的面积。 I / O焊盘（21）上的信号削波减少，功率消耗减少，芯片面积减少。
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5.发明申请公开(公告)号：US20070228475A1
公开(公告)日：2007-10-04
申请号：US11692722
申请日：2007-03-28
申请人： David C. Burdeaux , Daniel J. Lamey
发明人： David C. Burdeaux , Daniel J. Lamey
IPC分类号： H01L23/62
CPC分类号： H01L27/0255 , H01L29/0692 , H01L29/16 , H01L29/6609 , H01L29/861
摘要： An ESD protection circuit (20) includes an ESD device (24) and an isolation diode element (30). The ESD device includes a drain-source junction isolated ESD transistor (26,28). The isolation diode element is coupled in series with the ESD device and configured for providing ESD protection to a transistor device (22) needing ESD protection. Responsive to −Vgs conditions on a gate of the protected transistor device, the series coupled isolation diode element prevents a forward biasing of the drain-source junction of the ESD transistor prior to a breakdown condition of the isolation diode element. In addition, responsive to an ESD event sufficient to cause damage to the protected transistor device, the series coupled isolation diode element permits an occurrence of the breakdown condition. Furthermore, the ESD protection circuit can operate in both (i) a polarity of normal operation of the protected device and (ii) an opposite polarity other than in normal operation of the protected device.
摘要翻译： ESD保护电路（20）包括ESD器件（24）和隔离二极管元件（30）。 ESD器件包括漏 - 源结隔离ESD晶体管（26,28）。 隔离二极管元件与ESD器件串联耦合，并被配置为向需要ESD保护的晶体管器件（22）提供ESD保护。 响应于保护晶体管器件的栅极上的-Vgs条件，串联耦合隔离二极管元件在隔离二极管元件的击穿条件之前防止ESD晶体管的漏 - 源结的正向偏置。 此外，响应于足以导致对受保护的晶体管器件造成损害的ESD事件，串联耦合隔离二极管元件允许发生故障状态。 此外，ESD保护电路可以在（i）受保护器件的正常工作的极性和（ii）除了受保护器件的正常操作之外的相反极性的情况下工作。
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6.发明申请公开(公告)号：US20160181378A1
公开(公告)日：2016-06-23
申请号：US14572773
申请日：2014-12-17
申请人： Zihao M. Gao , David C. Burdeaux , Agni Mitra
发明人： Zihao M. Gao , David C. Burdeaux , Agni Mitra
CPC分类号： H01L29/7823 , H01L29/0611 , H01L29/0882 , H01L29/1087 , H01L29/1095 , H01L29/167 , H01L29/402 , H01L29/404 , H01L29/4175 , H01L29/66659 , H01L29/66712 , H01L29/7835
摘要： A transistor includes a surface region, a gate, a source dopant region, a drain dopant region, a drift dopant region, a set of electrically conductive shield plates, and a shield plate dopant region. A sidewall of the gate aligns with a drain side boundary of the surface region. The drain dopant region is within the surface region on the drain side. The drift dopant region is within the surface region between the drain side boundary and the drain dopant region. The set of electrically conductive shield plates includes a first shield plate overlying the drift dopant region. The shield plate dopant region is within the drift dopant region and underlies the set of shield plates.
摘要翻译： 晶体管包括表面区域，栅极，源极掺杂区域，漏极掺杂区域，漂移掺杂区域，一组导电屏蔽板以及屏蔽板掺杂区域。 栅极的侧壁与表面区域的漏极边界对准。 漏极掺杂剂区域在漏极侧的表面区域内。 漂移掺杂剂区域在漏极侧边界和漏极掺杂剂区域之间的表面区域内。 该组导电屏蔽板包括覆盖漂移掺杂剂区域的第一屏蔽板。 屏蔽板掺杂剂区域在漂移掺杂区域内并且位于该组屏蔽板之下。
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公开(公告)号：US08680615B2
公开(公告)日：2014-03-25
申请号：US13324910
申请日：2011-12-13
申请人： Agni Mitra , David C. Burdeaux
发明人： Agni Mitra , David C. Burdeaux
IPC分类号： H01L29/66
CPC分类号： H01L29/402 , H01L29/0692 , H01L29/404 , H01L29/4175 , H01L29/66719 , H01L29/7835
摘要： A customized shield plate field effect transistor (FET) includes a semiconductor layer, a gate dielectric, a gate electrode, and at least one customized shield plate. The shield plate includes a conductive layer overlying a portion of the gate electrode, one of the gate electrode sidewalls, and a portion of the substrate adjacent to the sidewall. The shield plate defines a customized shield plate edge at its lateral boundary. A distance between the customized shield plate edge and the sidewall of the gate electrode varies along a length of the sidewall. The customized shield plate edge may form triangular, curved, and other shaped shield plate elements. The configuration of the customized shield plate edge may reduce the area of the resulting capacitor and thereby achieve lower parasitic capacitance associated with the FET. The FET may be implemented as a lateral diffused MOS (LDMOS) transistor suitable for high power radio frequency applications.
摘要翻译： 定制的屏蔽板场效应晶体管（FET）包括半导体层，栅极电介质，栅极电极和至少一个定制的屏蔽板。 屏蔽板包括覆盖栅电极的一部分，栅极电极侧壁中的一个和与侧壁相邻的基板的一部分的导电层。 屏蔽板在其横向边界处限定了定制的屏蔽板边缘。 定制的屏蔽板边缘和栅电极的侧壁之间的距离沿侧壁的长度变化。 定制的屏蔽板边缘可以形成三角形，弯曲形和其他形状的屏蔽板元件。 定制的屏蔽板边缘的配置可以减小所得电容器的面积，从而实现与FET相关联的较低的寄生电容。 FET可以被实现为适合于高功率射频应用的横向漫射MOS（LDMOS）晶体管。
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公开(公告)号：US09123804B2
公开(公告)日：2015-09-01
申请号：US14302174
申请日：2014-06-11
IPC分类号： H01L29/76 , H01L29/94 , H01L31/113 , H01L31/119 , H01L29/78 , H01L29/66
CPC分类号： H01L29/7816 , H01L29/1045 , H01L29/1083 , H01L29/402 , H01L29/4175 , H01L29/66659 , H01L29/66681 , H01L29/78 , H01L29/7835 , Y02E10/50
摘要： A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and having a first conductivity type, a gate structure supported by the semiconductor substrate between the source and drain regions, a first well region in the semiconductor substrate, having a second conductivity type, and in which a channel region is formed under the gate structure during operation, and a second well region adjacent the first well region, having the second conductivity type, and having a higher dopant concentration than the first well region, to establish a path to carry charge carriers of the second conductivity type away from a parasitic bipolar transistor involving a junction between the channel region and the source region.
摘要翻译： 一种器件包括半导体衬底，半导体衬底中的源极和漏极区域，并且具有第一导电类型，由源极和漏极区域之间的半导体衬底支撑的栅极结构，半导体衬底中具有第二导电性的第一阱区域 类型，并且其中在操作期间在栅极结构下形成沟道区，以及与第一阱区相邻的具有第二导电类型并且具有比第一阱区更高的掺杂剂浓度的第二阱区，以建立路径 以承载第二导电类型的电荷载体，远离包含沟道区和源极区之间的结的寄生双极晶体管。
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公开(公告)号：US08772870B2
公开(公告)日：2014-07-08
申请号：US13665665
申请日：2012-10-31
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7816 , H01L29/1045 , H01L29/1083 , H01L29/402 , H01L29/4175 , H01L29/66659 , H01L29/66681 , H01L29/78 , H01L29/7835 , Y02E10/50
摘要： A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and having a first conductivity type, a gate structure supported by the semiconductor substrate between the source and drain regions, a well region in the semiconductor substrate, having a second conductivity type, and in which a channel region is formed under the gate structure during operation, and a shunt region adjacent the well region in the semiconductor substrate and having the second conductivity type. The shunt region has a higher dopant concentration than the well region to establish a shunt path for charge carriers of the second conductivity type that electrically couples the well region to a potential of the source region.
摘要翻译： 一种器件包括半导体衬底，半导体衬底中的源极和漏极区域，并具有第一导电类型，由源极和漏极区域之间的半导体衬底支撑的栅极结构，半导体衬底中的阱区，具有第二导电类型 并且其中在操作期间在栅极结构下方形成沟道区，以及与半导体衬底中的阱区相邻并具有第二导电类型的分流区。 并联区具有比阱区更高的掺杂浓度，以建立用于将阱区电耦合到源区的电位的第二导电类型的载流子的分流路径。
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公开(公告)号：US20140117446A1
公开(公告)日：2014-05-01
申请号：US13665665
申请日：2012-10-31
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7816 , H01L29/1045 , H01L29/1083 , H01L29/402 , H01L29/4175 , H01L29/66659 , H01L29/66681 , H01L29/78 , H01L29/7835 , Y02E10/50
摘要： A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and having a first conductivity type, a gate structure supported by the semiconductor substrate between the source and drain regions, a well region in the semiconductor substrate, having a second conductivity type, and in which a channel region is formed under the gate structure during operation, and a shunt region adjacent the well region in the semiconductor substrate and having the second conductivity type. The shunt region has a higher dopant concentration than the well region to establish a shunt path for charge carriers of the second conductivity type that electrically couples the well region to a potential of the source region.
摘要翻译： 一种器件包括半导体衬底，半导体衬底中的源极和漏极区域，并具有第一导电类型，由源极和漏极区域之间的半导体衬底支撑的栅极结构，半导体衬底中的阱区，具有第二导电类型 并且其中在操作期间在栅极结构下方形成沟道区，以及与半导体衬底中的阱区相邻并具有第二导电类型的分流区。 并联区具有比阱区更高的掺杂浓度，以建立用于将阱区电耦合到源区的电位的第二导电类型的载流子的分流路径。
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