Water Treatment Process and Plant Using Ballasted Flocculation and Settling
    2.
    发明申请
    Water Treatment Process and Plant Using Ballasted Flocculation and Settling 有权
    使用压载絮凝沉淀的水处理工艺和植物

    公开(公告)号:US20100096335A1

    公开(公告)日:2010-04-22

    申请号:US12521154

    申请日:2007-12-26

    IPC分类号: B01D21/34 B01D21/01 B01D21/08

    摘要: A method for treating wastewater using a ballasted flocculation technique includes continuously measuring the concentration of suspended solids, organic matter or other impurities in the water to be treated prior to directing the water to be treated to a flocculation tank. Based on this measurement, the amount of ballast necessary to obtain treated water of a predetermined quality is then calculated. In the flocculation tank, ballast and a flocculating reagent are added to the water to form a water-floc mixture. The water-floc mixture is directed to a settling tank where a sludge-ballast mixture is settled. The sludge-ballast mixture is directed to a mixing tank and then to a separator to separate the ballast from the sludge. The separated ballast is directed to the flocculation tank. The separated sludge is directed to the mixing tank when the level of sludge-ballast mixture in the mixing tank is lower than a predetermined level.

    摘要翻译: 使用压载絮凝技术处理废水的方法包括在将待处理的水引导到絮凝罐之前连续地测量被处理水中的悬浮固体,有机物质或其他杂质的浓度。 基于该测量,然后计算获得预定质量的处理水所需的压载量。 在絮凝槽中,将镇流器和絮凝剂添加到水中以形成水絮凝剂混合物。 将水絮凝物混合物导向沉淀池,在此沉淀池中沉淀有淤泥 - 镇流器混合物。 污泥 - 镇流器混合物被引导到混合罐,然后被引导到分离器以将淤渣与污泥分离。 分离的镇流器被引导到絮凝罐。 当混合罐中的污泥 - 镇流器混合物的水平低于预定水平时,分离的污泥被引导到混合槽。

    Water Treatment Process and Plant Using Ballasted Flocculation and Settling
    3.
    发明申请
    Water Treatment Process and Plant Using Ballasted Flocculation and Settling 有权
    使用压载絮凝沉淀的水处理工艺和植物

    公开(公告)号:US20140209523A1

    公开(公告)日:2014-07-31

    申请号:US14107071

    申请日:2013-12-16

    IPC分类号: C02F9/00 C02F1/52

    摘要: A method for treating wastewater using a ballasted flocculation technique includes continuously measuring the concentration of suspended solids, organic matter or other impurities in the water to be treated prior to directing the water to be treated to a flocculation tank. Based on this measurement, the amount of ballast necessary to obtain treated water of a predetermined quality is then calculated. In the flocculation tank, ballast and a flocculating reagent are added to the water to form a water-floc mixture. The water-floc mixture is directed to a settling tank where a sludge-ballast mixture is settled. The sludge-ballast mixture is directed to a mixing tank and then to a separator to separate the ballast from the sludge. The separated ballast is directed to the flocculation tank. The separated sludge is directed to the mixing tank when the level of sludge-ballast mixture in the mixing tank is lower than a predetermined level.

    摘要翻译: 使用压载絮凝技术处理废水的方法包括在将待处理的水引导到絮凝罐之前连续地测量被处理水中的悬浮固体,有机物质或其他杂质的浓度。 基于该测量,然后计算获得预定质量的处理水所需的压载量。 在絮凝槽中,将镇流器和絮凝剂添加到水中以形成水絮凝剂混合物。 将水絮凝物混合物导向沉淀池,在此沉淀池中沉淀有淤泥 - 镇流器混合物。 污泥 - 镇流器混合物被引导到混合罐,然后被引导到分离器以将淤渣与污泥分离。 分离的镇流器被引导到絮凝罐。 当混合罐中的污泥 - 镇流器混合物的水平低于预定水平时,分离的污泥被引导到混合槽。

    Method of fabricating integrated circuits having transistors and further semiconductor elements
    4.
    发明授权
    Method of fabricating integrated circuits having transistors and further semiconductor elements 有权
    制造具有晶体管和其它半导体元件的集成电路的方法

    公开(公告)号:US06436750B1

    公开(公告)日:2002-08-20

    申请号:US09645765

    申请日:2000-08-25

    申请人: Claus Dahl

    发明人: Claus Dahl

    IPC分类号: H01L218238

    摘要: Integrated transistors and other semiconductor elements are formed on a substrate. Spacers are applied for the purpose of producing LDD regions. A layer of polysilicon is first deposited in full-surface coverage and then removed except for spacers remaining on gate structures. The layer of polysilicon is utilized for the purpose of producing further integrated components and, for this purpose, is covered by an auxiliary layer and the latter in turn by an auxiliary mask. During the etching of the polysilicon layer, the structures covered by the auxiliary mask are preserved and can be utilized for further integrated components. The etching which is necessary for removing the spacers is effected selectively such that remaining structures of the auxiliary layer and thus of the underlying layer of polysilicon are not attacked. The components produced in addition are preserved. By slightly extending the process sequence for fabricating integrated transistors, a separate process block for fabricating the further integrated components is obviated.

    摘要翻译: 集成晶体管和其它半导体元件形成在衬底上。 垫片用于生产LDD区域。 首先将多晶硅层沉积在全表面覆盖层中,然后除去剩余在栅极结构上的间隔物。 多晶硅层用于生产另外的集成部件,为此目的被辅助层覆盖,而辅助层又由辅助掩模覆盖。 在蚀刻多晶硅层期间,保护由辅助掩模覆盖的结构,并且可以用于进一步的集成部件。 去除间隔物所需的蚀刻选择性地进行,使得辅助层的剩余结构以及因此的多晶硅的下层不被侵蚀。 另外生成的组分也被保留。 通过稍微扩展用于制造集成晶体管的工艺顺序,消除了用于制造另外的集成部件的单独的工艺块。

    Three-transistor DRAM cell and associated fabrication method
    5.
    发明授权
    Three-transistor DRAM cell and associated fabrication method 失效
    三晶体DRAM单元及相关制造方法

    公开(公告)号:US06661701B2

    公开(公告)日:2003-12-09

    申请号:US10158032

    申请日:2002-05-30

    IPC分类号: G11C1124

    CPC分类号: H01L27/108

    摘要: The three-transistor DRAM cell has a memory transistor formed as a field-effect transistor with a short-channel section and a long-channel section. A second insulating layer and a conductive layer are additionally formed on a gate layer of the memory transistor. A substantially constant voltage value is present between a potential of the conductive layer and a potential of the substrate area. A three-transistor DRAM cell with improved interference immunity and charge retention time

    摘要翻译: 三晶体管DRAM单元具有形成为具有短沟道部分和长沟道部分的场效应晶体管的存储晶体管。 另外在存储晶体管的栅极层上形成第二绝缘层和导电层。 在导电层的电位和衬底区域的电位之间存在基本恒定的电压值。 具有改善的抗干扰性和电荷保留时间的三晶体管DRAM单元

    Method for producing a planar spacer, an associated bipolar transistor and an associated BiCMOS circuit arrangement
    6.
    发明授权
    Method for producing a planar spacer, an associated bipolar transistor and an associated BiCMOS circuit arrangement 有权
    制造平面间隔物,相关双极晶体管和相关BiCMOS电路装置的方法

    公开(公告)号:US07709339B2

    公开(公告)日:2010-05-04

    申请号:US11553923

    申请日:2006-10-27

    IPC分类号: H01L21/331

    CPC分类号: H01L21/8249 H01L29/66242

    摘要: Method for producing a planar spacer, an associated bipolar transistor and an associated BiCMOS circuit arrangement. The invention relates to a method for production of a planar spacer, of an associated bipolar transistor and of an associated BiCMOS circuit arrangement, in which first and second spacer layers are formed after the formation of a sacrificial mask on a mount substrate. A first anisotropic etching process of the second spacer layer is carried out to produce auxiliary spacers. A second anisotropic etching step is then carried out, in order to produce the planar spacers, using the auxiliary spacers as an etch mask.

    摘要翻译: 制造平面间隔物,相关双极晶体管和相关BiCMOS电路装置的方法。 本发明涉及一种用于制造相关双极晶体管和相关BiCMOS电路装置的平面间隔件的方法,其中在安装基板上形成牺牲掩模之后形成第一和第二间隔层。 执行第二间隔层的第一各向异性蚀刻工艺以产生辅助间隔物。 然后,使用辅助间隔物作为蚀刻掩模,进行第二各向异性蚀刻步骤,以便产生平面间隔物。

    METHOD FOR PRODUCING A PLANAR SPACER, AN ASSOCIATED BIPOLAR TRANSISTOR AND AN ASSOCIATED BICMOS CIRCUIT ARRANGEMENT
    7.
    发明申请
    METHOD FOR PRODUCING A PLANAR SPACER, AN ASSOCIATED BIPOLAR TRANSISTOR AND AN ASSOCIATED BICMOS CIRCUIT ARRANGEMENT 有权
    生产平面间隔器,相关双极晶体管和相关BICMOS电路布置的方法

    公开(公告)号:US20070161176A1

    公开(公告)日:2007-07-12

    申请号:US11553923

    申请日:2006-10-27

    CPC分类号: H01L21/8249 H01L29/66242

    摘要: Method for producing a planar spacer, an associated bipolar transistor and an associated BiCMOS circuit arrangement. The invention relates to a method for production of a planar spacer, of an associated bipolar transistor and of an associated BiCMOS circuit arrangement, in which first and second spacer layers are formed after the formation of a sacrificial mask on a mount substrate. A first anisotropic etching process of the second spacer layer is carried out to produce auxiliary spacers. A second anisotropic etching step is then carried out, in order to produce the planar spacers, using the auxiliary spacers as an etch mask.

    摘要翻译: 制造平面间隔物,相关双极晶体管和相关BiCMOS电路装置的方法。 本发明涉及一种用于制造相关双极晶体管和相关BiCMOS电路装置的平面间隔件的方法,其中在安装基板上形成牺牲掩模之后形成第一和第二间隔层。 执行第二间隔层的第一各向异性蚀刻工艺以产生辅助间隔物。 然后,使用辅助间隔物作为蚀刻掩模,进行第二各向异性蚀刻步骤,以便产生平面间隔物。

    Method for manufacturing an integrated circuit and integrated circuit with a bipolar transistor and a hetero bipolar transistor
    8.
    发明申请
    Method for manufacturing an integrated circuit and integrated circuit with a bipolar transistor and a hetero bipolar transistor 有权
    用于制造具有双极晶体管和异质双极晶体管的集成电路和集成电路的方法

    公开(公告)号:US20050156193A1

    公开(公告)日:2005-07-21

    申请号:US10987952

    申请日:2004-11-12

    摘要: For the integration of an npn bipolar transistor with a hetero bipolar transistor, a placeholder layer is generated in a base region of the hetero bipolar transistor after structuring a collector structure for both types of transistors, wherein the placeholder layer is not present in a base region of the bipolar transistor. After generating the base of the bipolar transistor, the base of the bipolar transistor is covered, whereupon the placeholder layer is removed and the base of the hetero bipolar transistor is generated in the places where the placeholder layer has been removed. The emitter structure is again generated equally for both types of transistors so that an integrated circuit results which includes bipolar transistors and hetero bipolar transistors whose collector structures and/or whose emitter structures consist of identical production layers. Thus, space-saving and cost-effective integrated circuits may be produced benefiting from the advantages of both types of transistors.

    摘要翻译: 为了将npn双极晶体管与异质双极晶体管集成,在构造用于两种类型的晶体管的集电极结构之后,在异质双极晶体管的基极区域中产生占位符层,其中占位符层不存在于基极区域 的双极晶体管。 在产生双极晶体管的基极之后,双极晶体管的基极被覆盖,于是除去占位符层,并且在占位符层被去除的位置产生异质双极晶体管的基极。 对于两种类型的晶体管,再次产生发射极结构,使得集成电路的结果包括双极晶体管和异质双极晶体管,其集电极结构和/或其发射极结构由相同的生产层组成。 因此,可以利用两种类型的晶体管的优点来产生节省空间和成本有效的集成电路。

    Method for manufacturing an integrated circuit and integrated circuit with a bipolar transistor and a hetero bipolar transistor
    9.
    发明授权
    Method for manufacturing an integrated circuit and integrated circuit with a bipolar transistor and a hetero bipolar transistor 有权
    用于制造具有双极晶体管和异质双极晶体管的集成电路和集成电路的方法

    公开(公告)号:US07521733B2

    公开(公告)日:2009-04-21

    申请号:US10987952

    申请日:2004-11-12

    IPC分类号: H01L29/737

    摘要: For the integration of an npn bipolar transistor with a hetero bipolar transistor, a placeholder layer is generated in a base region of the hetero bipolar transistor after structuring a collector structure for both types of transistors, wherein the placeholder layer is not present in a base region of the bipolar transistor. After generating the base of the bipolar transistor, the base of the bipolar transistor is covered, whereupon the placeholder layer is removed and the base of the hetero bipolar transistor is generated in the places where the placeholder layer has been removed. The emitter structure is again generated equally for both types of transistors so that an integrated circuit results which includes bipolar transistors and hetero bipolar transistors whose collector structures and/or whose emitter structures consist of identical production layers. Thus, space-saving and cost-effective integrated circuits may be produced benefiting from the advantages of both types of transistors.

    摘要翻译: 为了将npn双极晶体管与异质双极晶体管集成,在构造用于两种类型的晶体管的集电极结构之后,在异质双极晶体管的基极区域中产生占位符层,其中占位符层不存在于基极区域 的双极晶体管。 在产生双极晶体管的基极之后,双极晶体管的基极被覆盖,于是除去占位符层,并且在占位符层被去除的位置产生异质双极晶体管的基极。 对于两种类型的晶体管,再次产生发射极结构,使得集成电路的结果包括双极晶体管和异质双极晶体管,其集电极结构和/或其发射极结构由相同的生产层组成。 因此,可以利用两种类型的晶体管的优点来产生节省空间和成本有效的集成电路。

    Method for producing a capacitor
    10.
    发明授权
    Method for producing a capacitor 有权
    电容器的制造方法

    公开(公告)号:US07091083B2

    公开(公告)日:2006-08-15

    申请号:US10888574

    申请日:2004-07-09

    IPC分类号: H01L21/8242

    摘要: A method for producing a capacitor comprises providing a raw structure having a substrate and at least one dielectric layer, wherein a first area and a second area of the substrate are separated by an isolating layer. Above the first and second areas, an electrically conductive layer is arranged on the at least one dielectric layer. Further, a mask layer is deposited on the electrically conductive layer, wherein it is structured for generating a first mask above the first area. The method further comprises etching away the electrically conductive layer and at least one of the dielectric layers in the second area by means of the first mask and completing an active device in the second area.

    摘要翻译: 制造电容器的方法包括提供具有基底和至少一个电介质层的原始结构,其中基底的第一区域和第二区域被隔离层隔开。 在第一和第二区域之上,导电层设置在至少一个电介质层上。 此外,掩模层沉积在导电层上,其中其被构造用于在第一区域上方产生第一掩模。 该方法还包括通过第一掩模蚀刻掉第二区域中的导电层和介电层中的至少一个,并在第二区域中完成有源器件。