公开(公告)号：US06903957B2

公开(公告)日：2005-06-07

申请号：US10863070

申请日：2004-06-08

申请人： Scott Derner ,  Casey Kurth ,  Phillip G. Wald

发明人： Scott Derner ,  Casey Kurth ,  Phillip G. Wald

IPC分类号： G11C11/401 ,  G11C11/404 ,  G11C17/12 ,  G11C17/00

CPC分类号： G11C11/404 ,  G11C17/12 ,  G11C2207/104

摘要： A half-density ROM embedded DRAM uses hard programmed non-volatile cells and unprogrammed dynamic cells. By hard programming either a first or second memory cell in a pair of cell, different data states are stored. Two word lines are used to access the memory cell pair. Because one of the cells is hard programmed, sense amplifier circuitry identifies the appropriate data state. The ROM cell can be programmed in numerous different manners. For example, ROM cells can be hard programmed by eliminating cell dielectric to short cell plates to a program voltage, or an electrical plug can be fabricated between the cell plates and shorted to a program voltage. In other embodiments, the ROM cell can be programmed using an anti-fuse programming technique, or by providing a high leakage path (not full short) such as through an active area to the substrate.

摘要翻译： 半密度ROM嵌入式DRAM使用硬编程的非易失性单元和未编程的动态单元。 通过对一对单元格中的第一或第二存储单元进行硬编程，存储不同的数据状态。 两条字线用于访问存储单元对。 因为其中一个单元是硬编程的，所以读出放大器电路识别适当的数据状态。 ROM单元可以以多种不同的方式进行编程。 例如，ROM单元可以通过将单元电池的电介质消除到编程电压来进行硬编程，或者可以在单元板之间制造电插头并且短路到编程电压。 在其他实施例中，ROM单元可以使用反熔丝编程技术进行编程，或者通过向衬底提供诸如通过有源区域的高泄漏路径（非完全短路）。

公开(公告)号：US06747889B2

公开(公告)日：2004-06-08

申请号：US10017658

申请日：2001-12-12

申请人： Scott Derner ,  Casey Kurth ,  Phillip G. Wald

发明人： Scott Derner ,  Casey Kurth ,  Phillip G. Wald

IPC分类号： G11C1700

CPC分类号： G11C11/404 ,  G11C17/12 ,  G11C2207/104

摘要： A half-density ROM embedded DRAM uses hard programmed non-volatile cells and unprogrammed dynamic cells. By hard programming either a first or second memory cell in a pair of cell, different data states are stored. Two word lines are used to access the memory cell pair. Because one of the cells is hard programmed, sense amplifier circuitry identifies the appropriate data state. The ROM cell can be programmed in numerous different manners. For example, ROM cells can be hard programmed by eliminating cell dielectric to short cell plates to a program voltage, or an electrical plug can be fabricated between the cell plates and shorted to a program voltage. In other embodiments, the ROM cell can be programmed using an anti-fuse programming technique, or by providing a high leakage path (not full short) such as through an active area to the substrate.

摘要翻译： 半密度ROM嵌入式DRAM使用硬编程的非易失性单元和未编程的动态单元。 通过对一对单元格中的第一或第二存储单元进行硬编程，存储不同的数据状态。 两条字线用于访问存储单元对。 因为其中一个单元是硬编程的，所以读出放大器电路识别适当的数据状态。 ROM单元可以以多种不同的方式进行编程。 例如，ROM单元可以通过将单元电池的电介质消除到编程电压来进行硬编程，或者可以在单元板之间制造电插头并且短路到编程电压。 在其他实施例中，ROM单元可以使用反熔丝编程技术进行编程，或者通过向衬底提供诸如通过有源区域的高泄漏路径（非完全短路）。

公开(公告)号：US06545899B1

公开(公告)日：2003-04-08

申请号：US10020371

申请日：2001-12-12

申请人： Scott Derner ,  Casey Kurth ,  Phillip G. Wald

发明人： Scott Derner ,  Casey Kurth ,  Phillip G. Wald

IPC分类号： G11C1700

CPC分类号： G11C7/14 ,  G11C7/06 ,  G11C17/12 ,  G11C17/18 ,  G11C2207/104

摘要： A ROM embedded DRAM that provides ROM cells that can be programmed to a single state. Bias techniques are used to read un-programmed ROM cells accurately. Sense amplifier circuitry can be offset in one embodiment to default to the un-programmed state. In another embodiment, bias circuitry is coupled to bit lines to favor the un-programmed state. Further, a differential pre-charge operation can also be used in another embodiment. The ROM embedded DRAM allows for simplifier fabrication and programming of the ROM cells, while providing accurate dual state functionality.

公开(公告)号：US06771529B2

公开(公告)日：2004-08-03

申请号：US10376768

申请日：2003-02-28

申请人： Scott Derner ,  Casey Kurth ,  Phillip G. Wald

发明人： Scott Derner ,  Casey Kurth ,  Phillip G. Wald

IPC分类号： G11C1700

CPC分类号： G11C7/14 ,  G11C7/06 ,  G11C17/12 ,  G11C17/18 ,  G11C2207/104

摘要： A ROM embedded DRAM that provides ROM cells that can be programmed to a single state. Bias techniques are used to read un-programmed ROM cells accurately. Sense amplifier circuitry can be offset in one embodiment to default to the un-programmed state. In another embodiment, bias circuitry is coupled to bit lines to favor the un-programmed state. Further, a differential pre-charge operation can also be used in another embodiment. The ROM embedded DRAM allows for simplifier fabrication and programming of the ROM cells, while providing accurate dual state functionality.

公开(公告)号：US06665207B2

公开(公告)日：2003-12-16

申请号：US09992203

申请日：2001-11-14

申请人： Phillip G. Wald ,  Casey Kurth ,  Scott Derner

发明人： Phillip G. Wald ,  Casey Kurth ,  Scott Derner

IPC分类号： G11C1124

CPC分类号： H01L27/10894 ,  G11C17/12 ,  H01L21/3144 ,  H01L21/31604 ,  H01L27/10852 ,  H01L27/112 ,  H01L27/11213 ,  H01L28/84

摘要： A ROM embedded DRAM allows hard programming of ROM cells by shorting DRAM capacitor plates during fabrication. In one embodiment, the intermediate dielectric layer is removed and the plates are shorted with a conductor. In another embodiment, an upper conductor and dielectric are removed and a conductor is fabricated in contact with the DRAM storage plate. The memory allows ROM cells to be hard programmed to different data states, such as Vcc and Vss.

公开(公告)号：US06603693B2

公开(公告)日：2003-08-05

申请号：US10017868

申请日：2001-12-12

申请人： Scott Derner ,  Casey Kurth ,  Phillip G. Wald

发明人： Scott Derner ,  Casey Kurth ,  Phillip G. Wald

IPC分类号： G11C702

CPC分类号： G11C7/14 ,  G11C11/4099

摘要： A DRAM improves cell read margins using bias, or reference, circuitry. The reference circuitry is coupled to a complimentary digit line to improve a differential voltage with an active digit line. One embodiment, improves one's margin by decreasing the complimentary digit line voltage. The reference circuitry can be an un-programmed DRAM cell, a non-volatile ROM memory cell or a conductor coupled to a reference voltage.

摘要翻译： DRAM使用偏置或参考电路来提高单元读取余量。 参考电路耦合到互补数字线，以利用有源数字线来提高差分电压。 一个实施例，通过减少补充数字线电压来提高余量。 参考电路可以是未编程的DRAM单元，非易失性ROM存储器单元或耦合到参考电压的导体。

公开(公告)号：US07366946B2

公开(公告)日：2008-04-29

申请号：US11702809

申请日：2007-02-06

申请人： Scott Derner ,  Casey Kurth ,  Phillip G. Wald

发明人： Scott Derner ,  Casey Kurth ,  Phillip G. Wald

IPC分类号： G06F11/00

CPC分类号： G11C29/822 ,  G11C11/401 ,  G11C17/14 ,  G11C29/74

摘要： Redundancy in a read only memory (ROM) embedded dynamic random access memory (DRAM) is accomplished by programming redundancy elements such as antifuses or registers with ROM data which is read instead of erroneous data. Multiple identical arrays of ROM bits can also be used for redundancy.

摘要翻译： 只读存储器（ROM）嵌入式动态随机存取存储器（DRAM）中的冗余通过编程冗余元件来实现，诸如反向熔丝或寄存器，ROM数据被读取而不是错误的数据。 多个相同的ROM位阵列也可用于冗余。

公开(公告)号：US07218547B2

公开(公告)日：2007-05-15

申请号：US10843161

申请日：2004-05-11

申请人： Casey Kurth ,  Scott Derner ,  Phillip G. Wald

发明人： Casey Kurth ,  Scott Derner ,  Phillip G. Wald

IPC分类号： G11C11/24

CPC分类号： G11C17/18 ,  G11C17/16

摘要： A ROM embedded DRAM provides ROM cells that can be electrically programmed to a data state using DRAM capacitor memory cells. Numerous techniques for reading the memory cells are provided if a single state memory is desired. For example, bias techniques allow un-programmed ROM cells to be read accurately. In one embodiment, the memory includes program circuitry to short capacitor plates together by breaking down an intermediate dielectric layer using anti-fuse programming techniques.

摘要翻译： ROM嵌入式DRAM提供可以使用DRAM电容器存储单元电可编程为数据状态的ROM单元。 如果需要单个状态存储器，则提供用于读取存储器单元的许多技术。 例如，偏置技术允许未编程的ROM单元被精确地读取。 在一个实施例中，存储器包括通过使用反熔丝编程技术分解中间介电层将电容器板短路在一起的程序电路。

公开(公告)号：US07099212B2

公开(公告)日：2006-08-29

申请号：US10924309

申请日：2004-08-23

申请人： Casey Kurth ,  Scott Derner ,  Phillip G. Wald

发明人： Casey Kurth ,  Scott Derner ,  Phillip G. Wald

IPC分类号： G11C7/00

CPC分类号： H01L27/10844 ,  G11C11/005 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10811 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11293

摘要： A ROM embedded DRAM provides ROM cells that can be programmed to a single state. The ROM cells include capacitors having a storage node. The storage node is processed to have a substantially high substrate leakage. The ROM cells, therefore, are hard programmed to a logic zero state. Bias techniques can be used to read un-programmed ROM cells accurately. As described, sense amplifier circuitry can be offset in one embodiment to default to the un-programmed state. In another embodiment, bias circuitry is coupled to bit lines to favor the un-programmed state. A differential pre-charge operation can also be used in another embodiment.

公开(公告)号：US07001816B2

公开(公告)日：2006-02-21

申请号：US10924416

申请日：2004-08-24

申请人： Casey Kurth ,  Scott Derner ,  Phillip G. Wald

发明人： Casey Kurth ,  Scott Derner ,  Phillip G. Wald

IPC分类号： H01L21/336

CPC分类号： H01L27/10844 ,  G11C11/005 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10811 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11293

摘要： A ROM embedded DRAM provides ROM cells that can be programmed to a single state. The ROM cells include capacitors having a storage node. The storage node is processed to have a substantially high substrate leakage. The ROM cells, therefore, are hard programmed to a logic zero state. Bias techniques can be used to read un-programmed ROM cells accurately. As described, sense amplifier circuitry can be offset in one embodiment to default to the un-programmed state. In another embodiment, bias circuitry is coupled to bit lines to favor the un-programmed state. A differential pre-charge operation can also be used in another embodiment.

摘要翻译： ROM嵌入式DRAM提供可以编程为单个状态的ROM单元。 ROM单元包括具有存储节点的电容器。 存储节点被处理以具有基本上高的衬底泄漏。 因此，ROM单元硬编程为逻辑0状态。 偏置技术可用于准确读取未编程的ROM单元。 如所描述的，读出放大器电路在一个实施例中可以被偏移到默认为未编程状态。 在另一个实施例中，偏置电路耦合到位线以有利于未编程状态。 差分预充电操作也可以在另一实施例中使用。