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公开(公告)号：US20050195010A1
公开(公告)日：2005-09-08
申请号：US11055564
申请日：2005-02-09
CPC分类号： H03H11/26 , H03K5/04 , H03K5/133 , H03K2005/00071 , H03K2005/00123 , H03K2005/00143 , H03K2005/00156 , H03K2005/00195
摘要： A time delay logic comprises a first stage with an inverter, a capacitor connected to the input terminal of the inverter, a constant current generator and an electronic switch controlled by an input pulse. The capacitor begins to charge at a predetermined edge of the input pulse and brings the input terminal of the inverter from a first voltage (ground) to the switching threshold voltage of the inverter, so that on the output terminal of the inverter there is obtained a pulse having an edge that, as referred to the predetermined edge of the input pulse, has a delay time that depends on the inverter threshold. The circuit comprises a second stage, coupled with the first, that is a dual circuit of the circuit of the first stage and has an inverter equal to the one of the first stage.
摘要翻译： 时间延迟逻辑包括具有逆变器的第一级，连接到逆变器的输入端的电容器，恒定电流发生器和由输入脉冲控制的电子开关。 电容器开始在输入脉冲的预定边沿充电，并将逆变器的输入端从第一电压（接地）转换到逆变器的开关阈值电压，从而在逆变器的输出端上获得 具有如参照输入脉冲的预定边缘具有取决于反相器阈值的延迟时间的边缘的脉冲。 电路包括与第一级耦合的第二级，即第一级的电路的双电路，并且具有等于第一级中的一级的反相器。
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公开(公告)号：US07425857B2
公开(公告)日：2008-09-16
申请号：US11055564
申请日：2005-02-09
IPC分类号： H03H11/26
CPC分类号： H03H11/26 , H03K5/04 , H03K5/133 , H03K2005/00071 , H03K2005/00123 , H03K2005/00143 , H03K2005/00156 , H03K2005/00195
摘要： A time delay logic comprises a first stage with an inverter, a capacitor connected to the input terminal of the inverter, a constant current generator and an electronic switch controlled by an input pulse. The capacitor begins to charge at a predetermined edge of the input pulse and brings the input terminal of the inverter from a first voltage (ground) to the switching threshold voltage of the inverter, so that on the output terminal of the inverter there is obtained a pulse having an edge that, as referred to the predetermined edge of the input pulse, has a delay time that depends on the inverter threshold. The circuit comprises a second stage, coupled with the first, that is a dual circuit of the circuit of the first stage and has an inverter equal to the one of the first stage.
摘要翻译： 时间延迟逻辑包括具有逆变器的第一级，连接到逆变器的输入端的电容器，恒定电流发生器和由输入脉冲控制的电子开关。 电容器开始在输入脉冲的预定边沿充电，并将逆变器的输入端从第一电压（接地）转换到逆变器的开关阈值电压，从而在逆变器的输出端上获得 具有如参照输入脉冲的预定边缘具有取决于反相器阈值的延迟时间的边缘的脉冲。 电路包括与第一级耦合的第二级，即第一级的电路的双电路，并且具有等于第一级中的一级的反相器。
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公开(公告)号：US10062457B2
公开(公告)日：2018-08-28
申请号：US13559537
申请日：2012-07-26
申请人： Federico Garibaldi
发明人： Federico Garibaldi
摘要： Methods for providing predictive notifications to a monitoring device are provided. In one aspect, a method includes receiving retrospective patient data collected from a plurality of medical devices, and determining, based on a comparison of the retrospective patient data with current patient data for a patient from a medical device, a likelihood of a potential adverse medical event occurring for the patient. The method also includes providing a notification to a monitoring device indicative of the potential adverse medical event for the patient. Systems, graphical user interfaces, and machine-readable media are also provided.
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公开(公告)号：US07280066B2
公开(公告)日：2007-10-09
申请号：US11423200
申请日：2006-06-09
申请人： Sergio Pernici , Federico Garibaldi
发明人： Sergio Pernici , Federico Garibaldi
IPC分类号： H03M1/12
摘要： A single-loop differential switched-capacitor sigma-delta converter has a three stage double-sampling architecture with reduced current consumption. The converter is stable for large input dynamics, which makes it suitable for RF applications. The three-stage multi-bit double-sampled architecture has a single-loop architecture in which all integrators are included in a same feedback loop. This has been made possible based upon the type of integrators that are connected in cascade. Functioning of the converter is less sensitive to nonlinearities of the operational amplifiers of the integrators.
摘要翻译： 单回路差分开关电容Σ-Δ转换器具有三级双采样架构，降低了电流消耗。 该转换器对于大输入动态稳定，使其适用于射频应用。 三级多位双采样架构具有单回路架构，其中所有积分器都包含在相同的反馈环路中。 这是基于级联的集成商的类型而实现的。 转换器的功能对集成商的运算放大器的非线性较不敏感。
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公开(公告)号：US20060279449A1
公开(公告)日：2006-12-14
申请号：US11423200
申请日：2006-06-09
申请人： Sergio Pernici , Federico Garibaldi
发明人： Sergio Pernici , Federico Garibaldi
IPC分类号： H03M1/12
摘要： A single-loop differential switched-capacitor sigma-delta converter has a three stage double-sampling architecture with reduced current consumption. The converter is stable for large input dynamics, which makes it suitable for RF applications. The three-stage multi-bit double-sampled architecture has a single-loop architecture in which all integrators are included in a same feedback loop. This has been made possible based upon the type of integrators that are connected in cascade. Functioning of the converter is less sensitive to nonlinearities of the operational amplifiers of the integrators.
摘要翻译： 单回路差分开关电容Σ-Δ转换器具有三级双采样架构，降低了电流消耗。 该转换器对于大输入动态稳定，使其适用于射频应用。 三级多位双采样架构具有单回路架构，其中所有积分器都包含在相同的反馈环路中。 这是基于级联的集成商的类型而实现的。 转换器的功能对集成商的运算放大器的非线性较不敏感。
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