公开(公告)号：US08692612B2

公开(公告)日：2014-04-08

申请号：US12891409

申请日：2010-09-27

申请人： Pierangelo Confalonieri ,  Federico Guanziroli ,  Germano Nicollini

发明人： Pierangelo Confalonieri ,  Federico Guanziroli ,  Germano Nicollini

IPC分类号： H03B1/00 ,  H03K5/00 ,  H04B1/10

CPC分类号： H03H5/12

摘要： The present disclosure relates to an electronic regulation device of a variable capacitance of an integrated circuit having a time parameter depending on the variable capacitance. The regulation device includes a regulation loop, and is configured to generate in output a plurality of binary regulation signals.

摘要翻译： 本公开涉及具有取决于可变电容的时间参数的集成电路的可变电容的电子调节装置。 调节装置包括调节回路，并且被配置为在输出中产生多个二进制调节信号。

公开(公告)号：US07675449B2

公开(公告)日：2010-03-09

申请号：US12172692

申请日：2008-07-14

申请人： Pierangelo Confalonieri ,  Marco Zamprogno ,  Riccardo Martignone

发明人： Pierangelo Confalonieri ,  Marco Zamprogno ,  Riccardo Martignone

IPC分类号： H03M1/66

CPC分类号： H03M1/0648 ,  H03M1/687 ,  H03M1/747

摘要： A current steering digital-analog converter for converting a digital code into an analog signal, the converter including a substrate of semiconductor material, an array of current generators integrated in the substrate, a common summation node and switches controllable on the basis of the digital code for connecting and disconnecting the current generators to and from the common summation node. The current generators are adapted to provide the common summation node with currents having a multiple value according to a power of two compared to a unit current value provided to the summation node by a current generator of the array of generators. The current generator is divided into a base number of modular current generation elements in parallel to one another at least equal to two.

摘要翻译： 一种用于将数字代码转换为模拟信号的电流转向数模转换器，所述转换器包括半导体材料的衬底，集成在衬底中的电流发生器的阵列，公共求和节点和基于数字代码可控的开关 用于将当前发生器连接到和从公共求和节点断开连接。 电流发生器适于根据与发电机阵列的电流发生器提供给求和节点的单位电流值相比的功率，为公共求和节点提供具有多个值的电流。 电流发生器被分成基本数量的模块化电流产生元件，彼此平行至少等于2。

公开(公告)号：US20050195010A1

公开(公告)日：2005-09-08

申请号：US11055564

申请日：2005-02-09

申请人： Pierangelo Confalonieri ,  Marco Zamprogno ,  Federico Garibaldi

发明人： Pierangelo Confalonieri ,  Marco Zamprogno ,  Federico Garibaldi

IPC分类号： H03B1/00 ,  H03H11/26 ,  H03K5/00 ,  H03K5/04 ,  H03K5/13

CPC分类号： H03H11/26 ,  H03K5/04 ,  H03K5/133 ,  H03K2005/00071 ,  H03K2005/00123 ,  H03K2005/00143 ,  H03K2005/00156 ,  H03K2005/00195

摘要： A time delay logic comprises a first stage with an inverter, a capacitor connected to the input terminal of the inverter, a constant current generator and an electronic switch controlled by an input pulse. The capacitor begins to charge at a predetermined edge of the input pulse and brings the input terminal of the inverter from a first voltage (ground) to the switching threshold voltage of the inverter, so that on the output terminal of the inverter there is obtained a pulse having an edge that, as referred to the predetermined edge of the input pulse, has a delay time that depends on the inverter threshold. The circuit comprises a second stage, coupled with the first, that is a dual circuit of the circuit of the first stage and has an inverter equal to the one of the first stage.

摘要翻译： 时间延迟逻辑包括具有逆变器的第一级，连接到逆变器的输入端的电容器，恒定电流发生器和由输入脉冲控制的电子开关。 电容器开始在输入脉冲的预定边沿充电，并将逆变器的输入端从第一电压（接地）转换到逆变器的开关阈值电压，从而在逆变器的输出端上获得 具有如参照输入脉冲的预定边缘具有取决于反相器阈值的延迟时间的边缘的脉冲。 电路包括与第一级耦合的第二级，即第一级的电路的双电路，并且具有等于第一级中的一级的反相器。

公开(公告)号：US06897801B2

公开(公告)日：2005-05-24

申请号：US10483790

申请日：2002-06-13

申请人： Pierangelo Confalonieri ,  Marco Zamprogno ,  Angelo Nagari

发明人： Pierangelo Confalonieri ,  Marco Zamprogno ,  Angelo Nagari

IPC分类号： H03M1/06 ,  H03M1/46 ,  H03M1/80 ,  H03M1/12 ,  G06F7/64 ,  G06G7/18 ,  G06G7/19

CPC分类号： H03M1/0682 ,  H03M1/468 ,  H03M1/804

摘要： An A/D converter having capacitors of a first array of sampling capacitors weighted in binary code connected between a first common circuit node and an input terminal to be charged to an input voltage with respect to a ground of a signal to be converted, and in accordance with SAR technique are then selectively connected with two differential reference terminals, and at the same time capacitors of a second array equal to the first and all connected to a second node are selectively connected to ground and the lower differential voltage terminal. The two nodes are connected to the respective inputs of a comparator. A logic unit controls the connections of the capacitors of the two arrays in accordance with a predetermined timing program and as a function of the output of the comparator.

摘要翻译： 一种A / D转换器，具有电容器，其具有以二进制代码加权的采样电容器的第一阵列阵列，连接在第一公共电路节点和待充电的输入端子之间，所述第一公共电路节点和输入端子相对于要转换的信号的接地为输入电压， 然后根据SAR技术选择性地与两个差分参考端子连接，并且同时等效于第一和所有连接到第二节点的第二阵列的电容器选择性地连接到地和下差分电压端子。 两个节点连接到比较器的相应输入端。 逻辑单元根据预定的定时程序和作为比较器的输出的函数来控制两个阵列的电容器的连接。

公开(公告)号：US5763907A

公开(公告)日：1998-06-09

申请号：US763937

申请日：1996-12-12

申请人： Carlo Dallavalle ,  Pierangelo Confalonieri

发明人： Carlo Dallavalle ,  Pierangelo Confalonieri

IPC分类号： H01L27/02 ,  H01L27/10

CPC分类号： H01L27/0207

摘要： A cell library for the design of integrated circuits, for example using CMOS technology, includes cells which define circuit modules in rectangular areas having an identical side. Two traces are provided which extend at right-angles to the identical side and which define strips for connection to the supply, at least one of which is in contact with the source regions of MOS transistors of a CMOS pair. In order to permit the design of integrated circuits in which the analog parts are insensitive to the noise induced in the substrate by the digital parts and in which it is possible to reduce the current absorption of the digital parts in stand-by mode, the cell library also provides a group of cells in which there is provided at least one additional trace which defines an additional strip for connection to the outside and which is in contact with the body regions of the MOS transistors of the CMOS pair.

摘要翻译： 用于设计集成电路的单元库，例如使用CMOS技术，包括在具有相同侧面的矩形区域中定义电路模块的单元。 提供了两条迹线，它们以直角延伸到同一侧，并且限定了用于连接到电源的条，其中至少一条与CMOS对的MOS晶体管的源极区域接触。 为了允许模拟部件对由数字部件在基板中感应的噪声不敏感的集成电路的设计，并且其中可以减少待机模式下的数字部件的电流吸收，电池 库还提供了一组单元，其中提供至少一个额外的迹线，其限定用于连接到外部并与CMOS对的MOS晶体管的体区接触的附加条。

公开(公告)号：US4883993A

公开(公告)日：1989-11-28

申请号：US279036

申请日：1988-12-02

申请人： Pierangelo Confalonieri ,  Sergio Pernici ,  Germano Nicollini

发明人： Pierangelo Confalonieri ,  Sergio Pernici ,  Germano Nicollini

IPC分类号： H03K5/1252

CPC分类号： H03K5/1252

摘要： The antibounce circuit comprises:(a) a first flip-flop constituted by a first and a second NAND gate (10, 12) having their respective outputs connected to one of the inputs of the other gate, the free input of the first gate being the input for said digital signal;(b) a second flip-flop constituted by a third and fourth NAND gate (14, 16) having their respective outputs connected to one of the inputs of the other gate, the free input of the third gate being connected to the output of the first gate;(c) a non-inverting delay circuit (20, 22, 24) connecting the output of the third gate to the free input of the second gate;(d) a first inverter connecting the output of the delay circuit to the free input of the fourth gate.

公开(公告)号：US4805192A

公开(公告)日：1989-02-14

申请号：US936369

申请日：1986-12-01

申请人： Pierangelo Confalonieri ,  Daniel Senderowicz ,  Augusto Tirelli

发明人： Pierangelo Confalonieri ,  Daniel Senderowicz ,  Augusto Tirelli

IPC分类号： H03K5/08 ,  H03M1/00 ,  H03M1/10 ,  H04B14/04 ,  H03M1/12

CPC分类号： H03M1/0607 ,  H03M1/825

摘要： In a Pulse Code Modulated (PCM) circuit chip, apparatus in the transmit path to compensate for an offset voltage signal from a band-pass filter includes an up-down counter which is actuated to provide a digital value equivalent to the offset signal and a digital to analog converter coupled to the counter to provide an analog signal representing the digital value in the counter. During an initialization phase, the counter is incremented until the digital value of the counter provides, by means of the digital to analog converter, an analog signal that compensates for the off-set signal. After the initialization phase when the band-pass filter's offset voltage is compensated, then other circuitry including an exclusive OR gate and an associated overflow counter are used to eneable or disable the up-down counter to insure that the PCM output signal is an accurate representation of the analog input signal. The up-down counter, during the operation phase following the initialization phase, is only enabled when the analog input signal is not present.

摘要翻译： 在脉冲编码调制（PCM）电路芯片中，用于补偿来自带通滤波器的偏移电压信号的传输路径中的装置包括被启动以提供与偏移信号等效的数字值的升降计数器，以及 数模转换器耦合到计数器以提供表示计数器中的数字值的模拟信号。 在初始化阶段期间，计数器递增，直到计数器的数字值通过数模转换器提供补偿偏移信号的模拟信号。 在对带通滤波器的偏移电压进行补偿的初始化阶段之后，使用包括异或门和相关联的溢出计数器的其它电路来使能或禁止升降计数器，以确保PCM输出信号是准确的表示 的模拟输入信号。 在初始化阶段之后的运行阶段，只有当模拟输入信号不存在时，才能使能上拉计数器。

公开(公告)号：US08427196B2

公开(公告)日：2013-04-23

申请号：US12893848

申请日：2010-09-29

申请人： Pierangelo Confalonieri ,  Federico Guanziroli ,  Marco Zamprogno

发明人： Pierangelo Confalonieri ,  Federico Guanziroli ,  Marco Zamprogno

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H03K17/162 ,  H03M1/0845 ,  H03M1/12 ,  H03M1/66 ,  Y10T307/50

摘要： A system includes analog supply circuitry providing first and second analog potentials. A switch module assumes first or second states to enable and inhibit transfer of an analog electrical signal from a source module to a user module based upon a driving electrical signal. A driving device drives, based upon the driving electrical signal, a control terminal of the switch module, allowing the switch module to assume the first or second state. The driving device allows the switch module to make a first driving transition from the first state to the second state, and a second driving transition from the second state to the first state. The driving device alternately connects the control terminal to a first reference potential, during the first state, and to a second reference potential, during the second state. The driving device connects the control terminal of the switch module to a third reference potential electrically distinct from the first and the second analog potentials, during each of the time intervals associated to the first or second driving transitions of the switch module.

摘要翻译： 系统包括提供第一和第二模拟电位的模拟电源电路。 开关模块基于驱动电信号，假设第一或第二状态来启用和禁止模拟电信号从源模块传送到用户模块。 驱动装置基于驱动电信号驱动开关模块的控制端子，允许开关模块呈现第一或第二状态。 驱动装置允许开关模块进行从第一状态到第二状态的第一驱动转变，以及从第二状态到第一状态的第二驱动转变。 在第二状态期间，驱动装置在第一状态期间交替地将控制端子连接到第一参考电位，并将第二参考电位交替地连接到第二参考电位。 在与开关模块的第一或第二驱动转换相关联的每个时间间隔期间，驱动装置将开关模块的控制端子连接到与第一和第二模拟电位电不同的第三参考电位。

公开(公告)号：US07888994B2

公开(公告)日：2011-02-15

申请号：US12395409

申请日：2009-02-27

申请人： Marco Zamprogno ,  Pierangelo Confalonieri ,  Alberto Minuti

发明人： Marco Zamprogno ,  Pierangelo Confalonieri ,  Alberto Minuti

IPC分类号： G06G7/12 ,  G06G7/26

CPC分类号： H03F3/005 ,  H03F3/45192 ,  H03F2203/45028 ,  H03F2203/45138 ,  H03F2203/45396 ,  H03F2203/45534 ,  H03F2203/45726

摘要： An electrical circuit for conversion from differential to single-ended includes a differential amplifier stage and first and second buffer circuits. The differential amplifier stage includes a first and a second input; and a first and a different second charging circuit that can be operatively coupled, respectively, with an output of the conversion circuit and with an auxiliary output. Each of the first and second buffer circuits is functionally arranged between one of said outputs and between one of said charging circuits. The buffer circuits being configured so as to substantially equalize relative impedances seen towards said outputs.

摘要翻译： 用于从差分到单端转换的电路包括差分放大器级和第一和第二缓冲电路。 差分放大器级包括第一和第二输入; 以及可以分别与转换电路的输出和辅助输出可操作地耦合的第一和第二充电电路。 第一和第二缓冲电路中的每一个功能地布置在所述输出之一和所述充电电路之一之间。 缓冲电路被配置为基本上相等于所述输出端所看到的相对阻抗。

公开(公告)号：US07501974B2

公开(公告)日：2009-03-10

申请号：US11832946

申请日：2007-08-02

申请人： Pierangelo Confalonieri ,  Marco Zamprogno ,  Francesca Girardi

发明人： Pierangelo Confalonieri ,  Marco Zamprogno ,  Francesca Girardi

IPC分类号： H03M1/12

CPC分类号： H03M1/0682 ,  H03M1/468 ,  H03M1/68 ,  H03M1/804

摘要： An analog/digital converter for converting an analog signal to a digital output code includes a local digital analog converter including a segmented array. The segmented array includes upper and lower segments of conversion elements selectively operable by respective digital command codes for respectively varying, according to binary weighted contributions, the voltages of first and second common nodes and the voltage of a second common node. A logic unit generates the digital command codes for controlling the local digital/analog converter according to a successive approximation technique for producing the digital output code. The converter includes a redistributor for modifying the command codes for redistributing the modified command codes between the lower segment and the upper segment, while making use of at least one auxiliary conversion element provided in the upper segment.

摘要翻译： 用于将模拟信号转换为数字输出代码的模拟/数字转换器包括具有分段阵列的本地数字模拟转换器。 分段阵列包括转换元件的上段和下段，其选择性地由相应的数字命令代码操作，以分别根据二进制加权贡献来改变第一和第二公共节点的电压和第二公共节点的电压。 逻辑单元根据用于产生数字输出代码的逐次逼近技术产生用于控制本地数字/模拟转换器的数字命令代码。 转换器包括再分配器，用于在使用在上段中提供的至少一个辅助转换元件的同时修改用于在下段和上段之间重新分配修改的命令代码的命令代码。