公开(公告)号：US06932617B2

公开(公告)日：2005-08-23

申请号：US10958890

申请日：2004-10-05

申请人： Pierre Debord ,  Rene Glaise ,  Claude Gomez

发明人： Pierre Debord ,  Rene Glaise ,  Claude Gomez

IPC分类号： H05K1/14 ,  H05K7/14 ,  H05K7/20 ,  H01R12/00

CPC分类号： H05K7/20563 ,  H05K1/14 ,  H05K7/1441 ,  H05K7/1444

摘要： A backplane system allowing a very large number of interconnections between high-connectivity printed circuit boards and a backplane is disclosed. The backplane is fragmented into a plurality of backplane parts that comprise connectors on their edges to mate connectors arranged on the high-connectivity printed circuit boards. These backplane parts may also include other connectors on their edges to couple to extension printed circuit boards requiring less interconnections or cables. Interposers can be used to link several backplane parts and provide enhanced air circulation.

公开(公告)号：US06824393B2

公开(公告)日：2004-11-30

申请号：US10152757

申请日：2002-05-22

申请人： Pierre Debord ,  Rene Glaise ,  Claude Gomez

发明人： Pierre Debord ,  Rene Glaise ,  Claude Gomez

IPC分类号： H01R1200

CPC分类号： H05K7/20563 ,  H05K1/14 ,  H05K7/1441 ,  H05K7/1444

摘要： A backplane system allowing a very large number of interconnections between high-connectivity printed circuit boards and a backplane is disclosed. The backplane is fragmented into a plurality of backplane parts that comprise connectors on their edges to mate connectors arranged on the high-connectivity printed circuit boards. These backplane parts may also include other connectors on their edges to couple to extension printed circuit boards requiring less interconnections or cables. Interposers can be used to link several backplane parts and provide enhanced air circulation.

摘要翻译： 公开了一种背板系统，其允许在高连通性印刷电路板和背板之间进行非常大量的互连。 背板被分割成多个背板部件，其包括在其边缘上的连接器，以配合在高连通性印刷电路板上的连接器。 这些背板部件还可以包括其边缘上的其它连接器，以耦合到需要较少互连或电缆的延伸印刷电路板。 内插器可用于连接多个背板部件，并提供增强的空气循环。

公开(公告)号：US20050042893A1

公开(公告)日：2005-02-24

申请号：US10958890

申请日：2004-10-05

申请人： Pierre Debord ,  Rene Glaise ,  Claude Gomez

发明人： Pierre Debord ,  Rene Glaise ,  Claude Gomez

IPC分类号： H05K1/14 ,  H05K7/14 ,  H05K7/20 ,  H01R12/00

CPC分类号： H05K7/20563 ,  H05K1/14 ,  H05K7/1441 ,  H05K7/1444

摘要： A backplane system allowing a very large number of interconnections between high-connectivity printed circuit boards and a backplane is disclosed. The backplane is fragmented into a plurality of backplane parts that comprise connectors on their edges to mate connectors arranged on the high-connectivity printed circuit boards. These backplane parts may also include other connectors on their edges to couple to extension printed circuit boards requiring less interconnections or cables. Interposers can be used to link several backplane parts and provide enhanced air circulation.

摘要翻译： 公开了一种背板系统，其允许在高连通性印刷电路板和背板之间进行非常大量的互连。 背板被分割成多个背板部件，其包括在它们的边缘上的连接器，以配合设置在高连通性印刷电路板上的连接器。 这些背板部件还可以包括其边缘上的其它连接器，以耦合到需要较少互连或电缆的延伸印刷电路板。 内插器可用于连接多个背板部件，并提供增强的空气循环。

公开(公告)号：US4961193A

公开(公告)日：1990-10-02

申请号：US276583

申请日：1988-11-28

申请人： Pierre Debord ,  Rene Glaise

发明人： Pierre Debord ,  Rene Glaise

IPC分类号： G06F11/10 ,  G06F12/16 ,  H03M13/00 ,  H03M13/19

CPC分类号： G06F11/1028 ,  H03M13/19

摘要： An apparatus and method for correcting data words from a memory is provided in which coded data is divided into a plurality of multi-bit packages of b bits each. The coded data comprises n-bit words with r error correcting code bits and n-r data bits. The invention is capable of correcting one package which has suffered at least one hard failure and a single soft error located in a different package. The invention involves the use of an error correcting code which gives a first syndrome when the data word has suffered a first error coming from at least one error in a first package and a single error in a different second package, which also gives a second syndrome when the data word has suffered a second error coming from at least one error in the above first package, and a single error in a third package. The error correcting code is such that equality of the first and second syndromes results in the equality of the first and second errors.

公开(公告)号：US06452900B1

公开(公告)日：2002-09-17

申请号：US09207061

申请日：1998-12-07

申请人： Alain Blanc ,  Bernard Brezzo ,  Pierre Debord ,  Albert Widmer

发明人： Alain Blanc ,  Bernard Brezzo ,  Pierre Debord ,  Albert Widmer

IPC分类号： H04L100

CPC分类号： H04L47/263 ,  H04L12/5602 ,  H04L47/10 ,  H04L49/255 ,  H04L49/3081 ,  H04L49/45 ,  H04L49/506 ,  H04L2012/5615 ,  H04L2012/563 ,  H04L2012/5635

摘要： A flow control process for a switching architecture having a central switch core with associated distributed Switch Core Access Layers communicating with the core by means of serial data communication links. The serial links carry data flows that are coded in accordance with the 8B/10B coding, where two among the three comma characters are used for creating an additional specialized flow control channel. When the cells are idle or empty, the nature of the comma character that appears at the beginning of the cell provides the appropriate flow control bit information. For instance, should the K.28.5 character be detected, the receiving entity (either the switching structure or a distributed SCAL element) decodes the character as positive flow control information, corresponding to a request to reduce the incoming data flow. Also, should the K.28.1 character be decoded, then the receiving entity decodes this as information according to which no reduction in the data flow is requested. When the incoming flow provides data cells, the invention uses a predetermined bit within the data cell, generally that immediately following the beginning of the cell, in order to carry the flow control information.

摘要翻译： 一种用于具有中央交换机核心的交换架构的流控制过程，其具有通过串行数据通信链路与核心通信的相关联的分布式交换机核心接入层。 串行链路携带根据8B / 10B编码编码的数据流，其中三个逗号中的两个用于创建附加的专用流控制信道。 当单元格空闲或空闲时，出现在单元开头的逗号字符的性质提供了适当的流控制位信息。 例如，如果检测到K.28.5字符，接收实体（交换结构或分布式SCAL元素）将该字符解码为正流量控制信息，对应于减少传入数据流的请求。 此外，如果解码了K.28.1字符，则接收实体将其解码为信息，根据该信息不要求数据流的减少。 当传入流提供数据单元时，本发明使用数据单元内的预定位，通常是在单元开始之后，为了承载流量控制信息。

公开(公告)号：US4145721A

公开(公告)日：1979-03-20

申请号：US764100

申请日：1977-01-31

申请人： Pierre L. Beaudouin ,  Pierre Debord

发明人： Pierre L. Beaudouin ,  Pierre Debord

IPC分类号： A61B6/03 ,  H04N1/401 ,  H04N5/217 ,  H04N3/14 ,  H01L27/14 ,  H03B1/00

CPC分类号： H04N5/2173 ,  A61B6/032 ,  H04N1/401

摘要： A noise reduction scheme for a photosensitive self scan system includes an array of photosensitive elements producing video signals and first and second pluralities of switching elements, one element of each of the pluralities of switching elements being connected to one photosensitive element of the array. A first video line connects each element of the first plurality of switching elements to a first input terminal of a summing device such as a differential amplifier and a second video line connects each element of the second plurality of switching elements to a second input terminal of the differential amplifier. Shift register means operated by clock pulses is provided to control the operation of each of the elements of the first plurality of switching elements to sequentially couple the photosensitive elements to the first input terminal and to apply periodically only clock pulse noise signals through the gate drain capacitance of the second plurality of switching elements to the second input terminal of the differential amplifier, so as to produce at the output of the amplifier a video signal substantially free of noise signals created by the clock pulses.

摘要翻译： 用于感光自扫描系统的降噪方案包括产生视频信号的光敏元件阵列和第一和第二多个开关元件，多个开关元件中的每一个的一个元件连接到该阵列的一个感光元件。 第一视频线将第一多个开关元件的每个元件连接到诸如差分放大器的求和装置的第一输入端，而第二视频线将第二多个开关元件的每个元件连接到第二输入端 差分放大器。 提供由时钟脉冲操作的移位寄存器装置以控制第一多个开关元件的每个元件的操作，以顺序地将感光元件耦合到第一输入端子，并且周期性地施加时钟脉冲噪声信号通过栅极漏极电容 的第二多个开关元件连接到差分放大器的第二输入端，以便在放大器的输出处产生基本上没有由时钟脉冲产生的噪声信号的视频信号。

公开(公告)号：US06343081B1

公开(公告)日：2002-01-29

申请号：US09121992

申请日：1998-07-24

申请人： Alain Blanc ,  Bernard Brezzo ,  Pierre Debord ,  Patrick Jeanniot ,  Alain Saurel

发明人： Alain Blanc ,  Bernard Brezzo ,  Pierre Debord ,  Patrick Jeanniot ,  Alain Saurel

IPC分类号： H04L1256

CPC分类号： H04L49/3081 ,  H04L12/5601 ,  H04L49/1507 ,  H04L49/1553 ,  H04L49/201 ,  H04L49/25 ,  H04L49/506 ,  H04L2012/5679

摘要： A method and apparatus for managing contention in a self-routing switching architecture based on a set of n×n individual switching structures that are connected in a port expansion mode by means of fan-out and fan-in circuits providing access of the Switch Core Access Layer (SCAL) to the different input and output ports of the switching core. The fan-in circuits use an arbitration mechanism for providing a token to the switch that is allowed to deliver the next cell and the arbiter operates from a detection of a special comma character in accordance with the 8B/10B coding scheme which is introduced in the data flow between the individual switching structures and the fan-in circuits. This provides a compensation for the difference in transfer delays of the cells even when high switching speed and long length of the physical media are involved.

摘要翻译： 一种用于管理自路由交换架构中的争用的方法和装置，所述方法和装置基于通过扇出方式连接的端口扩展模式的一组nxn个别交换结构，以及提供交换机核心接入层 （SCAL）到交换核心的不同输入和输出端口。 扇入电路使用仲裁机制，用于向交换机提供令牌，该令牌被允许传送下一个小区，并且仲裁器根据在8B中引入的8B / 10B编码方案的特殊逗号字符的检测来操作 各个开关结构和扇入电路之间的数据流。 即使涉及物理介质的高切换速度和长的长度，这也为单元的传送延迟的差异提供了补偿。

公开(公告)号：US4251803A

公开(公告)日：1981-02-17

申请号：US912123

申请日：1978-06-02

申请人： Pierre Debord ,  Jean-Louis Marijon

发明人： Pierre Debord ,  Jean-Louis Marijon

IPC分类号： H03M1/10 ,  H03F1/30 ,  H03F3/00 ,  H03F3/38 ,  H03M1/00 ,  H03K13/02

CPC分类号： H03F1/304 ,  H03M1/1295

摘要： Disclosed is a dynamic compensation circuit for correcting the residual offset voltage encountered in an analog-to-digital conversion chain. Samples of an analog signal having an average value equal to 0 are provided to a first input of a comparator, the second input of which receives a reference signal generated through a D to A converter under control of a control logic circuit. A sample and hold circuit with the comparator causes a DC offset of the output signal level which is to be dynamically corrected by the compensating circuit of the invention. The DC offset causes the duty cycle to differ from one by an amount .DELTA.DC which will be the error curve signal of the compensation circuit. The compensating circuit reduces the .DELTA.DC to 0 by adding to the signal a DC voltage opposite to and of equal magnitude to the offset voltage level.

摘要翻译： 公开了用于校正在模数转换链中遇到的残余失调电压的动态补偿电路。 具有等于​​0的平均值的模拟信号的样本被提供给比较器的第一输入，其比较器的第一输入在控制逻辑电路的控制下接收通过D转换器A产生的参考信号。 具有比较器的采样和保持电路引起将由本发明的补偿电路动态校正的输出信号电平的DC偏移。 直流偏移导致占空比不同于一个量程DELTA DC，这将是补偿电路的误差曲线信号。 补偿电路通过向信号增加与偏移电压电平相反且等于幅度的DC电压，将DELTA DC减小到0。

公开(公告)号：US06606300B1

公开(公告)日：2003-08-12

申请号：US09219081

申请日：1998-12-22

申请人： Alain Blanc ,  Pierre Debord ,  Alain Saurel ,  Bernard Brezzo

发明人： Alain Blanc ,  Pierre Debord ,  Alain Saurel ,  Bernard Brezzo

IPC分类号： H04L1256

CPC分类号： H04L49/3081 ,  H04L49/1507 ,  H04L49/201 ,  H04L49/25 ,  H04L49/50 ,  H04L49/506 ,  H04L2012/563 ,  H04L2012/5672 ,  H04Q11/0478

摘要： A flow control process for a switching system having at least one switch core connected through serial communication links to remote and distributed Protocol Adapters or Protocol Engines through Switch Core Access Layer (SCAL) elements. For each input port i, the SCAL element contains a receive Protocol Interface corresponding to the adapter assigned to the input port i and a first serializer for providing attachment to the switch core by means of a first serial communication link. When the cells are received in the switch core, they are deserialized by means of a first deserializer. At each output port, the cells are serialized again by means of a second serializer and then transmitted via a second serial communication link, to the appropriate SCAL. The SCAL contains a second deserializer and a transmit Protocol Interface circuit for permitting attachment of the Protocol Adapter. The flow control process permits two flow control signals, a flow control receive (FCR) from the core to the SCAL, and a flow control transmit (FCX) from the SCAL back to the core. For transmission of the FCR signal in response to the detection of local saturation in the switch core, the process causes transfer of an internal FCR signal to the serializer located within the saturated core. The FCR is introduced in the normal data flow to be conveyed through the second serial link to the remote SCAL corresponding to the saturated input port of the core. An internal control signal can be transmitted to the Protocol Interface that is originating too many cells which results in the overloaded input port of the core. For the transmission of the FCX signal in response to the detection of a saturated Protocol Interface element at one output port, the process generates an internal control signal to the serializer located in the SCAL element. The serializer can introduce a FCX signal in the normal data flow which is conveyed to the core and then decoded by the deserializer in the core. Thus, the core can be informed of the saturation condition that has occurred in the considered output port. Particular adaptations are provided in which the switching system is arranged in a set of individual switching structures mounted in a port expansion mode.

公开(公告)号：US4380005A

公开(公告)日：1983-04-12

申请号：US139329

申请日：1980-04-11

申请人： Pierre Debord ,  Jean-Louis Marijon

发明人： Pierre Debord ,  Jean-Louis Marijon

IPC分类号： H03M1/10 ,  H03F1/30 ,  H03F3/00 ,  H03F3/38 ,  H03M1/00 ,  H03K13/02

CPC分类号： H03F1/304 ,  H03M1/1295

摘要： Disclosed is a dynamic compensation circuit for correcting the residual offset voltage encountered in an analog-to-digital conversion chain. Samples of an analog signal having an average value equal to 0 are provided to a first input of a comparator, the second input of which receives a reference signal generated through a D to A converter under control of a control logic circuit. A sample and hold circuit with the comparator causes a DC offset of the output signal level which is to be dynamically corrected by the compensating circuit of the invention. The DC offset causes the duty cycle to differ from one by an amount .DELTA.DC which will be the error curve signal of the compensation circuit. The compensating circuit reduces the .DELTA.DC to 0 by adding to the signal a DC voltage opposite to and of equal magnitude to the offset voltage level.

摘要翻译： 公开了用于校正在模数转换链中遇到的残余失调电压的动态补偿电路。 具有等于​​0的平均值的模拟信号的样本被提供给比较器的第一输入，其比较器的第一输入在控制逻辑电路的控制下接收通过D转换器A产生的参考信号。 具有比较器的采样和保持电路引起将由本发明的补偿电路动态校正的输出信号电平的DC偏移。 直流偏移导致占空比不同于一个量程DELTA DC，这将是补偿电路的误差曲线信号。 补偿电路通过向信号增加与偏移电压电平相反且等于幅度的DC电压，将DELTA DC减小到0。