利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

81 条记录 (耗时 0.03 秒)

    Low power programming technique for a floating body memory transistor, memory cell, and memory array
    1.
    发明授权
    Low power programming technique for a floating body memory transistor, memory cell, and memory array 有权

    公开(公告)号：US07177175B2

    公开(公告)日：2007-02-13

    申请号：US11334338

    申请日：2006-01-17

    申请人： Pierre Fazan ,  Serguei Okhonin

    发明人： Pierre Fazan ,  Serguei Okhonin

    IPC分类号： G11C11/24 ,  H01L27/01

    CPC分类号： G11C11/404 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/7841

    摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a memory cell, architecture, and/or array and/or technique of writing or programming data into the memory cell (for example, a technique to write or program a logic low or State “0” in a memory cell employing an electrically floating body transistor. In this regard, the present invention programs a logic low or State “0” in the memory cell while the electrically floating body transistor is in the “OFF” state or substantially “OFF” state (for example, when the device has no (or practically no) channel and/or channel current between the source and drain). In this way, the memory cell may be programmed whereby there is little to no current/power consumption by the electrically floating body transistor and/or from memory array having a plurality of electrically floating body transistors.

    Semiconductor device
    3.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07541616B2

    公开(公告)日：2009-06-02

    申请号：US11975862

    申请日：2007-10-22

    申请人： Pierre Fazan ,  Serguei Okhonin

    发明人： Pierre Fazan ,  Serguei Okhonin

    IPC分类号： H01L31/112

    CPC分类号： H01L27/108 ,  G11C11/403 ,  G11C11/404 ,  G11C11/5621 ,  G11C2211/4016 ,  H01L21/84 ,  H01L27/10802 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841 ,  H04N5/3355 ,  Y10S257/905 ,  Y10S257/907 ,  Y10S438/982

    摘要： A semiconductor integrated circuit device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate and the drain and between the source and the drain.

    摘要翻译： 公开了一种半导体集成电路器件，例如存储器件或放射线检测器，其中数据存储单元形成在衬底上。 每个数据存储单元包括具有源极，漏极和栅极的场效应晶体管，以及布置在源极和漏极之间的用于存储在体内产生的电荷的主体。 体内净电荷的大小可以通过施加到晶体管的输入信号来调节，并且可以通过在栅极和漏极之间施加电压信号来至少部分地抵消由输入信号调节净电荷 在源和漏之间。

    Semiconductor device
    4.
    发明申请
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US20080073719A1

    公开(公告)日：2008-03-27

    申请号：US11977705

    申请日：2007-10-25

    申请人： Pierre Fazan ,  Serguei Okhonin

    发明人： Pierre Fazan ,  Serguei Okhonin

    IPC分类号： H01L27/108 ,  H01L27/12

    CPC分类号： H01L27/108 ,  G11C11/403 ,  G11C11/404 ,  G11C11/5621 ,  G11C2211/4016 ,  H01L21/84 ,  H01L27/10802 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841 ,  H04N5/3355 ,  Y10S257/905 ,  Y10S257/907 ,  Y10S438/982

    摘要： A semiconductor integrated circuit device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate and the drain and between the source and the drain.

    摘要翻译： 公开了一种半导体集成电路器件，例如存储器件或放射线检测器，其中数据存储单元形成在衬底上。 每个数据存储单元包括具有源极，漏极和栅极的场效应晶体管，以及布置在源极和漏极之间的用于存储在体内产生的电荷的主体。 体内净电荷的大小可以通过施加到晶体管的输入信号来调节，并且可以通过在栅极和漏极之间施加电压信号来至少部分地抵消由输入信号调节净电荷 在源和漏之间。

    Semiconductor device
    5.
    发明申请
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US20080055974A1

    公开(公告)日：2008-03-06

    申请号：US11975862

    申请日：2007-10-22

    申请人： Pierre Fazan ,  Serguei Okhonin

    发明人： Pierre Fazan ,  Serguei Okhonin

    IPC分类号： G11C11/34

    CPC分类号： H01L27/108 ,  G11C11/403 ,  G11C11/404 ,  G11C11/5621 ,  G11C2211/4016 ,  H01L21/84 ,  H01L27/10802 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841 ,  H04N5/3355 ,  Y10S257/905 ,  Y10S257/907 ,  Y10S438/982

    摘要： A semiconductor integrated circuit device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between-the gate and the drain and between the source and the drain.

    摘要翻译： 公开了一种半导体集成电路器件，例如存储器件或放射线检测器，其中数据存储单元形成在衬底上。 每个数据存储单元包括具有源极，漏极和栅极的场效应晶体管，以及布置在源极和漏极之间的用于存储在体内产生的电荷的主体。 可以通过施加到晶体管的输入信号来调节身体中的净电荷的幅度，并且可以通过在栅极和栅极之间施加电压信号来至少部分地抵消通过输入信号调整净电荷 漏极和源极与漏极之间。

    Semiconductor device
    9.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US06969662B2

    公开(公告)日：2005-11-29

    申请号：US10450238

    申请日：2002-06-05

    申请人： Pierre Fazan ,  Serguei Okhonin

    发明人： Pierre Fazan ,  Serguei Okhonin

    IPC分类号： G01T1/24 ,  G11C11/403 ,  G11C11/404 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/786 ,  H01L31/10 ,  H01L21/336

    CPC分类号： H01L27/108 ,  G11C11/403 ,  G11C11/404 ,  G11C11/5621 ,  G11C2211/4016 ,  H01L21/84 ,  H01L27/10802 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841 ,  H04N5/3355 ,  Y10S257/905 ,  Y10S257/907 ,  Y10S438/982

    摘要： A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate 13. Each of the data storage cells includes a field effect transistor having a source 18, drain 22 and gate 28, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body 22 can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate 28 and the drain 22 and between the source 18 and the drain 22.

    摘要翻译： 公开了诸如存储器件或辐射检测器的半导体器件，其中数据存储单元形成在衬底13上。 每个数据存储单元包括具有源极18，漏极22和栅极28的场效应晶体管，以及布置在源极和漏极之间的用于存储在体内产生的电荷的主体。 主体22中的净电荷的大小可以通过施加到晶体管的输入信号进行调整，并且可以通过在栅极28和栅极28之间施加电压信号来至少部分地抵消由输入信号调节净电荷 漏极22和源极18与漏极22之间。

    Low power programming technique for a floating body memory transistor, memory cell, and memory array
    10.
    发明申请
    Low power programming technique for a floating body memory transistor, memory cell, and memory array 有权
    用于浮体存储晶体管，存储单元和存储器阵列的低功耗编程技术

    公开(公告)号：US20050063224A1

    公开(公告)日：2005-03-24

    申请号：US10941692

    申请日：2004-09-15

    申请人： Pierre Fazan ,  Serguei Okhonin

    发明人： Pierre Fazan ,  Serguei Okhonin

    IPC分类号： G11C11/404 ,  H01L27/108 ,  G11C11/34

    CPC分类号： G11C11/404 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/7841

    摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a memory cell, architecture, and/or array and/or technique of writing or programming data into the memory cell (for example, a technique to write or program a logic low or State “0” in a memory cell employing an electrically floating body transistor. In this regard, the present invention programs a logic low or State “0” in the memory cell while the electrically floating body transistor is in the “OFF” state or substantially “OFF” state (for example, when the device has no (or practically no) channel and/or channel current between the source and drain). In this way, the memory cell may be programmed whereby there is little to no current/power consumption by the electrically floating body transistor and/or from memory array having a plurality of electrically floating body transistors.

    摘要翻译： 这里描述和说明了许多发明。 在一个方面，本发明涉及将数据写入或编程到存储器单元中的存储器单元，架构和/或阵列和/或技术（例如，写入或编程逻辑低或状态“0”的技术 在这方面，本发明在电浮动体晶体管处于“关”状态或基本上“关”的情况下，在存储单元中编程逻辑低或状态“0” 状态（例如，当器件在源极和漏极之间没有（或几乎不存在）通道和/或沟道电流）时，可以对存储器单元进行编程，由此存储单元很少或没有电流/功耗 电浮体晶体管和/或具有多个电浮体晶体管的存储器阵列。