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公开(公告)号：US5058134A
公开(公告)日：1991-10-15
申请号：US397949
申请日：1989-08-24
CPC分类号： H04L27/3455 , H04J3/0605
摘要： In data transmission wherein a transmitting modem transmits data signals to a receiving modem via a telephone line, the process of rotating, in the transmitting modem, the phase of the point of the constellation resulting from a group of data bits by a predetermined phase value, and then rotating, after a predetermined delay in the receiving modem, the phase of the estimated point resulting from the transformation of the analog signal by the opposite of said predetermined phase value, and calculating the mean-squared error between the rotated point and the estimated point of the constellation the error being used to determine whether the receiving modem is out of synchronization.
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公开(公告)号：US5031195A
公开(公告)日：1991-07-09
申请号：US361174
申请日：1989-06-05
CPC分类号： H04L25/03044 , H03H21/0018
摘要： Fully adaptive modem receiver for data-transmission systems which use trellis-coded modulation (TCM) and comprises an adaptive whitened-matched filter (WMF) and a reduced-state trellis decoder. The WMF consists of an adaptive linear equalizer with fractional-T spaced coefficients, and an adaptive linear predictor. The decoder combines the functions of equalization and TCM decoding. It employs combined intersymbol interference (ISI) and code states which exploit the set-partitioning structure of the underlying TCM code to provide full or reduced-state information about past ISI terms. The decoder branch metric cancels those ISI terms that are not, or are only partially, represented by the trellis states.
摘要翻译： 用于使用网格编码调制（TCM）并且包括自适应白化匹配滤波器（WMF）和缩减状态网格解码器的数据传输系统的完全自适应调制解调器接收机。 WMF由具有分数T间隔系数的自适应线性均衡器和自适应线性预测器组成。 解码器结合了均衡和TCM解码的功能。 它采用组合符号间干扰（ISI）和代码状态，利用底层TCM代码的集合分区结构来提供关于过去ISI术语的完整或简化状态信息。 解码器分支度量取消不是或仅部分地由网格状态表示的那些ISI术语。
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公开(公告)号：US4775988A
公开(公告)日：1988-10-04
申请号：US888598
申请日：1986-07-23
CPC分类号： H04L27/08 , H03G3/3068 , H03G3/3089
摘要： For adaptively adjusting the gain in a modem receiver comprising two amplifiers (15, 19), the following steps are performed: for a buffer (21), a Hilbert filter (23), and an equalizer (27), a respective energy indicator (P.sub.max.sup.2, u.sub.avg.sup.2, x.sub.avg.sup.2) is generated from the signal samples in the respective delay line. Each energy indicator is compared to an associataed upper target level (4L.sub.U, 3L.sub.P, 1.19 L.sub.X), and for the equalizer also to an associated lower target level (0.84 L.sub.X). If necessary, a gain correction factor (S) initially set to 1.0 is modified to obtain an overall gain that keeps delay line energies within desired targets. Target comparisons are made so that excess energy in the buffer or Hilbert filter result in a rapid gain reduction whereas average equilizer energy is used for slow adaptations. After a gain change, all acquired samples in the delay lines are also multiplied by the correction factor (S) so that none is lost during gain acquisition. Gain is distributed between the two amplifiers in a swapping operation without modifying the adjusted overall gain.
摘要翻译： 为了自适应地调整包括两个放大器（15,19）的调制解调器接收机的增益，执行以下步骤：对于缓冲器（21），希尔伯特滤波器（23）和均衡器（27），相应的能量指示器 Pmax2，uavg2，xavg2）从相应延迟线中的信号样本产生。 每个能量指示器与相关的上部目标水平（4LU，3LP，1.19 LX）进行比较，并且对于均衡器也与相关联的较低目标水平（0.84LX）进行比较。 如果需要，修改初始设置为1.0的增益校正因子（S）以获得将延迟线能量保持在期望目标内的总增益。 进行目标比较，使得缓冲器或希尔伯特滤波器中的过剩能量导致快速增益减小，而平均平衡能量用于缓慢适应。 在增益变化之后，延迟线中的所有获取样本也被乘以校正因子（S），使得在增益获取期间没有丢失。 在交换操作中，增益分布在两个放大器之间，而不改变调整后的总体增益。
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4.发明授权公开(公告)号：US06181683B2
公开(公告)日：2001-01-30
申请号：US08973264
申请日：1997-12-03
IPC分类号： H04B7216
CPC分类号： H04L1/0065 , H04J13/00 , H04L1/0057 , H04L1/0059 , H04L1/0071 , H04L1/1867 , H04W8/26 , H04W28/065 , H04W48/08 , H04W52/367 , H04W52/50 , H04W60/00 , H04W74/004 , H04W74/0825 , H04W74/0833
摘要： A system and method for the wireless transmission of data packets in a code division multiple access communication system wherein one of the code division multiple access channels (PRCH) is used in a time-shared fashion for the transmission of the data packets from several transmitting stations (MSy, MSz) to a receiving station (BS). A request is sent from a transmitting station (MSy) to the corresponding receiving station (BS) of the communication system indicating the destination address to which data packet(s) are to be routed. Then, registering the transmitting station (MSy) and assigning an unique virtual connection identifier (VCIy) to it. Next, the transmitting station (MSy) is attached to the code division multiple access channel (PRCH) used for the transmission of data packets. Then, listening to the downlink of the code division multiple access channel (PRCH) used for the transmission of data packets until the corresponding receiving station (BS) broadcasts that it will be “idle” such that a random access to the code division multiple access channel (PRCH) used for the transmission of data packets is allowed in the next frame. Next, the transnmission power of the transmitting station (MSy) is ramped up during the next frame until a certain power level is reached. The data packet(s) and the virtual connection identifier (VCIy) are transmitted over the uplink of the code division multiple access channel (PRCH) used for the transmission of data packets to the receiving station (BS). The data packet(s) are routed to the destination address. Access to the code division multiple access channel (PRCH) used for the transmission of data packets is controller by a multiple access protocol based on carrier sensing and collision detection (CSMA/CD).
摘要翻译： 一种用于在码分多址通信系统中无线传输数据分组的系统和方法，其中码分多址信道（PRCH）中的一个以时分方式用于从多个发射台发送数据分组 （MSy，MSz）到接收站（BS）。请求从发送站（MSy）发送到通信系统的相应接收站（BS），指示数据分组将要的目的地地址 然后，注册发送站（MSy）并向其分配唯一的虚拟连接标识符（VCIy）。接下来，发送站（MSy）附加到用于数据传输的码分多址信道（PRCH） 然后，监听用于数据分组传输的码分多址信道（PRCH）的下行链路，直到相应的接收站（BS）广播它将为“空闲” 使得在下一帧中允许对用于传输数据分组的码分多址信道（PRCH）的随机访问。接下来，发送站（MSy）的传输功率在下一帧期间增加，直到 数据包和虚拟连接标识符（VCIy）通过用于向接收站（BS）发送数据包的码分多址信道（PRCH）的上行链路发送。 数据包被路由到目的地址。用于传输数据包的码分多址信道（PRCH）的访问是基于载波侦听和冲突检测（CSMA / CD）的多址协议的控制器， 。
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公开(公告)号：US5113401A
公开(公告)日：1992-05-12
申请号：US400415
申请日：1989-08-30
CPC分类号： H04L27/3433 , H04L27/3477
摘要： In a trellis-coded modulation (TCM) transmission system, data bits are grouped into bit blocks (13), and each such bit block is encoded to select a fixed number w of symbols from a given symbol set (14). The symbols are subdivided into subsets, and each subset includes a few outer symbols and a greater number of inner symbols. Each symbol represents one particular transmission signal value. A first portion (17) of each bit block is separated into w bit subgroups, each of which is separately expanded by a convolutional encoder (20) to obtain a bit combination (19, 15) for specifying one of the symbol subsets. The remaining portion (21) of each bit block is expanded by a block coder (22) to obtain w bit subgroups (23), each being a bit combination (25, 16) for selecting one particular symbol out of a specified subset; outer symbols are selected less frequently than inner symbols. The arrangement allows to transmit a non-integer number of data bits per symbol, and further allows to operate with single-symbol TCM.
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6.发明授权Microprocessor including means for concurrently copying ALU results into selected operand register subsets and at least one main memory locations 失效微处理器包括用于同时将ALU结果复制到选择的操作数寄存器子集和至少一个主存储器位置的装置
公开(公告)号：US4615004A
公开(公告)日：1986-09-30
申请号：US681047
申请日：1984-12-13
CPC分类号： G06F9/30032 , G06F15/786
摘要： A microprocessor having a single common data bus (17) to which the output (33) of the arithmetic-logic unit (11) as well as input and output of the data memory (13) are connected without intermediate buffer registers. Of the working registers (21, 23, 25, 27) connected to the ALU inputs, one group (21, 23) is loaded from the common data bus and the other group (25, 27), used as accumulators, is directly loaded from the ALU output. Specific control circuitry (51, 53, 55, 57, 59, 61) allows selective storing of ALU output values into accumulators (25, 27), and simultaneous transfer with selective scaling into another register and into an addressed memory location within the same cycle during which the instruction was executed.
摘要翻译： 具有单个公共数据总线（17）的微处理器，算术逻辑单元（11）的输出（33）以及数据存储器（13）的输入和输出连接到其上，而没有中间缓冲寄存器。 在连接到ALU输入的工作寄存器（21,23,25,27）中，从公共数据总线加载一组（21,23），并且用作累加器的另一组（25,27）被直接加载 从ALU输出。 特定控制电路（51,53,55,57,59,61）允许将ALU输出值选择性地存储到累加器（25,27）中，并且通过选择性缩放同时传送到另一个寄存器并在同一周期内的寻址存储器位置 执行指令期间。
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7.发明授权Arithmetic device for concurrently summing two series of products from two sets of operands 失效用于从两组操作数中同时求和两个系列产品的算术装置
公开(公告)号：US4490807A
公开(公告)日：1984-12-25
申请号：US556760
申请日：1983-12-01
CPC分类号： H03H17/06 , G06F17/15 , G06F7/5443
摘要： In a signal processor computing arrangement comprising an ALU (11) and a multiplier (21), two selectively usable accumulators (37, 41) and gating circuitry (61, 63) are provided to allow alternating computation and accumulation of product terms for two output values with sets of input values that overlap. This saves memory accesses by using the same operand twice for different output values, and requires only one processor cycle per partial term and output value. A specific pipeline multiplier (21) is provided consisting of two partial sections (29, 31) with an intermediate pipeline register (33) to allow applying a second set of input operands while computation of the product of a first set of operands is still in progress.
摘要翻译： 在包括ALU（11）和乘法器（21）的信号处理器计算装置中，提供两个可选择使用的累加器（37,41）和选通电路（61,63），以允许用于两个输出的产品项的交替计算和积累 值与重叠的输入值集合。 这可以通过对不同的输出值使用相同的操作数两次来节省存储器访问，并且每个部分项和输出值只需要一个处理器周期。 提供由具有中间流水线寄存器（33）的两个部分部分（29,31）组成的特定流水线乘法器（21），以允许应用第二组输入操作数，同时第一组操作数的乘积的计算仍然在 进展。
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8.发明授权Method of transmitting binary data sequences and arrangement for enabling the rapid determination of the end of a transmitted binary data sequence 失效发送二进制数据序列的方法和用于能够快速确定所发送的二进制数据序列的结束的装置
公开(公告)号：US4447908A
公开(公告)日：1984-05-08
申请号：US327006
申请日：1981-12-03
CPC分类号： H04L5/16 , H04L1/0083 , H04L27/3433
摘要： A communication method and arrangement are disclosed which provide, for a trellis encoding process in the transmitter and a maximum-likelihood decoding process in the receiver, an additional fifth state (ZS) in addition to the usual four coding states (S0 . . . S3). The fifth state is entered in the transmitter at the end of transmission when a particularly selected escape symbol from a set of four escape symbols (E0 . . . E3) each associated to one of the four normal coding states is sent by an encoder supplement (15). In the receiver, a stop signal indicating end of transmission is only generated when, after the usual decoder delay, a path decoder (63) determines that an escape symbol was received, and a trellis decoder (61) indicates the fifth state (ZS) to be the most probable one. This enables rapid and secure determination of the end of a transmitted sequence without the need for additional transmission symbols or decoder cycles.
摘要翻译： 公开了一种通信方法和装置，其针对发射机中的网格编码处理和接收机中的最大似然解码处理，除了通常的四种编码状态之外还提供附加的第五状态（ZS）（S ... S3 ）。 当从四个正常编码状态之一相关联的一组四个转义符号（E0。。。E3）中特别选择的转义符号由编码器补充（发送）发送时，第五状态在发送结束时被输入到发送器中 15）。 在接收机中，仅当在通常的解码器延迟之后路径解码器（63）确定接收到转义符号时，才产生指示发送结束的停止信号，并且网格解码器（61）指示第五状态（ZS） 成为最可能的一个。 这使得能够快速和安全地确定发送序列的结束，而不需要额外的传输符号或解码器周期。
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9.发明授权Method and arrangement for detecting the presence of a training signal in a modem receiver 失效用于检测调制解调器接收机中训练信号的存在的方法和装置
公开(公告)号：US4674103A
公开(公告)日：1987-06-16
申请号：US888295
申请日：1986-07-22
CPC分类号： H04L27/01 , H04L27/066
摘要： For rapidly detecting a periodic training signal in a modem receiver, delay line storage (21) is provided for a signal section which is equal to one training signal period (q.multidot.M samples) plus an additional adjacent window (q.multidot.W samples). Thus, the stored signal section includes two windows (17', 19) which are offset by one training signal period and which are similar if a training signal is present. In evaluation means (41) connected to the two windows (17', 19), two auxiliary signals (z.sub.1, z.sub.2) are generated (61, 65) which represent the signal energy and the correlation, respectively, of the samples in the two windows. From the auxiliary signals, a dissimilarity metric (z.sub.3) is derived (69) and is compared (73) to a given threshold for generating an indicator signal (CYC) which becomes active when a training signal is present, i.e. when the two window contents are similar and the metric (z.sub.3) falls below the threshold. A carrier frequency offset estimate (.DELTA..sub.f) is also derived from the second auxiliary signal (z.sub.2).
摘要翻译： 为了快速检测调制解调器接收机中的周期性训练信号，为等于一个训练信号周期（q×M个样本）加上附加的相邻窗口（q×W个样本）的信号部分提供延迟线存储器（21）。 因此，存储的信号部分包括被一个训练信号周期偏移的两个窗口（17'，19），并且如果存在训练信号则这两个相似。 在连接到两个窗口（17'，19）的评估装置（41）中，生成两个辅助信号（z1，z2），分别表示两个样本中的信号能量和相关性 视窗。 从辅助信号中，导出不同度量（z3）（69）并与（73）比较（73）给定阈值，以产生当存在训练信号时变为有效的指示信号（CYC），即当两个窗口内容 是相似的，度量（z3）低于阈值。 还从第二辅助信号（z2）导出载波频率偏移估计（DELTA f）。
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公开(公告)号：US4400616A
公开(公告)日：1983-08-23
申请号：US293069
申请日：1981-08-17
申请人： Pierre R. Chevillat , Fritz Gfeller
发明人： Pierre R. Chevillat , Fritz Gfeller
IPC分类号： G02B6/12 , B42D15/10 , G02B6/34 , G03H1/04 , G06K1/12 , G06K19/16 , G07D7/00 , G07D7/20 , G07F7/08 , G06K19/06
CPC分类号： G07D7/0013 , G06K1/126 , G06K19/16 , G07D7/20 , G07F7/086 , G03H1/0011 , G03H1/0408 , G03H2222/47 , Y10S283/901
摘要： An identification card provided with secret data contained in the form of a wave guide hologram recorded in a layer on the card. Light for developing or displaying the hologram is introduced into a wave guide layer extending along the surface of the card through a grating that admits light only of a given wave length suitable for developing the wave guide hologram. The secrecy of the wave guide hologram is further enhanced by incorporating into the light coupling grating a further hologram by which light only of a predetermined pattern can be coupled to the wave guide for delivery to the wave guide hologram.
摘要翻译： 提供有以记录在卡上的层中的波导全息图形式包含的秘密数据的识别卡。 用于显影或显示全息图的光被引入通过光栅延伸的波导层中，该光栅仅允许适合于显影波导全息图的给定波长的光。 通过在光耦合光栅中并入另外的全息图，进一步增强了波导全息图的保密性，通过该另外的全息图，只有预定图案的光可以耦合到波导以传送到波导全息图。
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