公开(公告)号：US20100100514A1

公开(公告)日：2010-04-22

申请号：US12260511

申请日：2008-10-29

申请人： Pierre Raymond ,  Guy Paillet ,  Anne Menendez

发明人： Pierre Raymond ,  Guy Paillet ,  Anne Menendez

IPC分类号： G06N3/02

CPC分类号： G06K9/6271 ,  G06K9/00771 ,  G08B13/00

摘要： A sensor unit comprising a sensor, a neural processor and a communication device, wherein the sensor unit is adapted to perform pattern recognition by means of the neural processor and to transfer the result of the pattern recognition via the communication device.

摘要翻译： 一种传感器单元，包括传感器，神经处理器和通信设备，其中所述传感器单元适于通过所述神经处理器执行模式识别，并且经由所述通信设备传送所述模式识别的结果。

公开(公告)号：US08478081B2

公开(公告)日：2013-07-02

申请号：US12880964

申请日：2010-09-13

申请人： Guy Paillet ,  Anne Menendez

发明人： Guy Paillet ,  Anne Menendez

IPC分类号： G06K7/00

CPC分类号： G06K9/2027 ,  G06K9/00973 ,  G06K9/78 ,  H04N5/335 ,  H04N5/3355

摘要： The present invention is directed to an apparatus which can acquire, readout and perceive a scene based on the insertion, or embedding of photosensitive elements into or on a transparent or semi-transparent substrate such as glass or plastic. The substrate itself may act as the optical device which deflects the photons of an incident image into the photosensitive elements. A digital neural memory can be trained to recognize patterns in the incident photons. The photosensitive elements and digital neural memory elements may be arranged with light elements controlled in accordance with the patterns detected. In one application, intelligent lighting units provide light while monitoring surroundings and/or adjusting light according to such surroundings. In another application, intelligent displays display images and/or video while monitoring surroundings and/or adjusting the displayed images and/or video in accordance with such surroundings.

公开(公告)号：US07796841B2

公开(公告)日：2010-09-14

申请号：US11477571

申请日：2006-06-30

申请人： Guy Paillet ,  Anne Menendez

发明人： Guy Paillet ,  Anne Menendez

IPC分类号： G06K9/20

CPC分类号： G06K9/00973 ,  G06K9/78

摘要： An apparatus which can acquire, readout and perceive a scene based on the insertion, or etching of photosensitive elements into or on a transparent or semi-transparent substrate such as glass. The substrate itself acts as the optical device which deflects the photons incident to the reflected image into the photosensitive elements. Photosensitive elements are interconnected together by a transparent or opaque wiring. A digital neural memory can be trained to recognize specific scenery such as a human face, an incoming object, a surface defect, rain drops on a windshield and more. Other applications include image-perceptive car headlight and flat panel display detecting and identifying the viewer's behavior (gaze tracking, face recognition, facial expression recognition and more). Yet another application includes sliding doors perceiving the direction and speed of an individual coming towards that door. Yet another application includes permanent damage detection (texture change) in dam, bridge or other manmade construction.

摘要翻译： 可以基于将光敏元件插入或蚀刻到透明或半透明基板（例如玻璃）中或之上而获取，读出和感知场景的装置。 衬底本身用作将入射到反射图像的光子偏转到感光元件中的光学装置。 感光元件通过透明或不透明的布线互连在一起。 可以训练数字神经记忆以识别诸如人脸，进入物体，表面缺陷，挡风玻璃上的雨滴等特定风景。 其他应用包括图像感知车头灯和平板显示器，用于检测和识别观众的行为（凝视跟踪，脸部识别，面部表情识别等）。 另一个应用包括滑动门感知到达该门的个人的方向和速度。 另一种应用包括大坝，桥梁或其他人造建筑物的永久性损伤检测（纹理变化）。

公开(公告)号：US20070014469A1

公开(公告)日：2007-01-18

申请号：US11477571

申请日：2006-06-30

申请人： Guy Paillet ,  Anne Menendez

发明人： Guy Paillet ,  Anne Menendez

IPC分类号： G06K9/62

CPC分类号： G06K9/00973 ,  G06K9/78

摘要： An apparatus which can acquire, readout and perceive a scene based on the insertion, or etching of photosensitive elements into or on a transparent or semi-transparent substrate such as glass. The substrate itself acts as the optical device which deflects the photons incident to the reflected image into the photosensitive elements. Photosensitive elements are interconnected together by a transparent or opaque wiring. A digital neural memory can be trained to recognize specific scenery such as a human face, an incoming object, a surface defect, rain drops on a windshield and more. Other applications include image-perceptive car headlight and flat panel display detecting and identifying the viewer's behavior (gaze tracking, face recognition, facial expression recognition and more). Yet another application includes sliding doors perceiving the direction and speed of an individual coming towards that door. Yet another application includes permanent damage detection (texture change) in dam, bridge or other manmade construction.

摘要翻译： 可以基于将光敏元件插入或蚀刻到透明或半透明基板（例如玻璃）中或之上而获取，读出和感知场景的装置。 衬底本身用作将入射到反射图像的光子偏转到感光元件中的光学装置。 感光元件通过透明或不透明的布线互连在一起。 可以训练数字神经记忆以识别诸如人脸，进入物体，表面缺陷，挡风玻璃上的雨滴等特定风景。 其他应用包括图像感知车头灯和平板显示器，用于检测和识别观众的行为（凝视跟踪，脸部识别，面部表情识别等）。 另一个应用包括滑动门感知到达该门的个人的方向和速度。 另一种应用包括大坝，桥梁或其他人造建筑物的永久性损伤检测（纹理变化）。

公开(公告)号：US06606614B1

公开(公告)日：2003-08-12

申请号：US09648302

申请日：2000-08-24

申请人： Guy Paillet ,  Donald F. Specht

发明人： Guy Paillet ,  Donald F. Specht

IPC分类号： G06F1500

CPC分类号： G06N3/063

摘要： A neural network integrated circuit comprises many neuron circuits each with a distance resister that is compared in a competition for the closest-hit with all the other neurons. Such closest-hit comparison is conducted bit-by-bit over the many bit positions of a distance measure in binary format each time after the neurons fire. A single-wire AND-bus interconnects every neuron in a whole system. Each neuron drives the single-wire AND-bus with an open-collector buffer. All neurons press the single-wire AND-bus with their respective distance measures in successive cycles, starting with the most significant bit. For example, a fourteen-bit binary distance word requires fourteen comparison cycles. Any neuron that sees a “0” on the single-wire AND-bus when its own corresponding bit in its distance measure is a “1”, automatically drops from the competition. By the time the least significant bit cycle is run, a single closest distance will have been determined. Such neuron that wins announces itself with an identifying code.

摘要翻译： 神经网络集成电路包括许多神经元电路，每个具有距离电阻的神经元电路在与所有其他神经元的最接近的命中的竞争中进行比较。 在神经元发射之后，这种最接近的比较是在二进制格式的距离测量的许多位位置上逐位进行的。 单线AND总线将整个系统中的每个神经元互连。 每个神经元都使用集电极开路缓冲器驱动单线AND总线。 所有神经元在连续周期内按照单线AND总线按照相应的距离测量，从最高有效位开始。 例如，十四位二进制距离字需要十四个比较周期。 任何在单线AND总线上看到“0”的神经元当其距离测量中自己的相应位为“1”时，自动从竞争中掉落。 在运行最低有效位周期的时候，将确定单个最近的距离。 获胜的这样的神经元用识别码宣布自己。

公开(公告)号：US5701397A

公开(公告)日：1997-12-23

申请号：US485336

申请日：1995-06-07

申请人： Andre Steimle ,  Didier Louis ,  Guy Paillet

发明人： Andre Steimle ,  Didier Louis ,  Guy Paillet

IPC分类号： G06F15/18 ,  G06N3/00 ,  G06N3/04 ,  G06N3/06 ,  G06N3/063

CPC分类号： G06K9/6271 ,  G06K9/00986 ,  G06N3/063

摘要： In each neuron in a neural network of a plurality of neuron circuits either in an engaged or a free state, a pre-charge circuit, that allows loading the components of an input vector (A) only into a determined free neuron circuit during a recognition phase as a potential prototype vector (B) attached to the determined neuron circuit. The pre-charge circuit is a weight memory (251) controlled by a memory control signal (RS) and the circuit generating the memory control signal. The memory control signal identifies the determined free neuron circuit. During the recognition phase, the memory control signal is active only for the determined free neuron circuit. When the neural network is a chain of neuron circuits, the determined free neuron circuit is the first free neuron in the chain. The input vector components on an input data bus (DATA-BUS) are connected to the weight memory of all neuron circuits. The data therefrom are available in each neuron on an output data bus (RAM-BUS). The pre-charge circuit may further include an address counter (252) for addressing the weight memory and a register (253) to latch the data output on the output data bus. After the determined neuron circuit has been engaged, the contents of its weight memory cannot be modified. Pre-charging the input vector during the recognition phase makes the engagement process more efficient and significantly reduces learning time in learning the input vector.

摘要翻译： 在接合或自由状态下的多个神经元电路的神经网络中的每个神经元中，预充电电路允许在识别期间将输入矢量（A）的分量加载到确定的自由神经元电路中 相作为附着到确定的神经元电路的潜在原型载体（B）。 预充电电路是由存储器控制信号（RS）控制的重量存储器（251）和产生存储器控制信号的电路。 存储器控制信号识别确定的自由神经元电路。 在识别阶段期间，存储器控制信号仅对所确定的自由神经元电路有效。 当神经网络是神经元电路链时，确定的游离神经元电路是链中的第一个游离神经元。 输入数据总线（DATA-BUS）上的输入向量分量连接到所有神经元电路的权重存储器。 其数据可在输出数据总线（RAM-BUS）上的每个神经元中使用。 预充电电路还可以包括用于寻址权重存储器的地址计数器（252）和用于锁存输出数据总线上的数据的寄存器（253）。 在确定的神经元电路被接合之后，其重量记忆的内容不能被修改。 在识别阶段对输入向量进行预充电，使得参与过程更有效，并显着减少学习输入向量的学习时间。

公开(公告)号：US5740326A

公开(公告)日：1998-04-14

申请号：US486658

申请日：1995-06-07

申请人： Jean-Yves Boulet ,  Pascal Tannhof ,  Guy Paillet

发明人： Jean-Yves Boulet ,  Pascal Tannhof ,  Guy Paillet

IPC分类号： G06F15/18 ,  G06F7/544 ,  G06N3/00 ,  G06N3/04 ,  G06N3/06 ,  G06N3/063

CPC分类号： G06K9/6271 ,  G06F7/544 ,  G06N3/063 ,  G06K2209/01

摘要： In a neural network of N neuron circuits, having an engaged neuron's calculated p bit wide distance between an input vector and a prototype vector and stored in the weight memory thereof, an aggregate search/sort circuit (517) of N engaged neurons' search/sort circuits. The aggregate search/sort circuit determines the minimum distance among the calculated distances. Each search/sort circuit (502-1) has p elementary search/sort units connected in series to form a column, such that the aggregate circuit is a matrix of elementary search/sort units. The distance bit signals of the same bit rank are applied to search/sort units in each row. A feedback signal is generated by ORing in an OR gate (12.1) all local search/sort output signals from the elementary search/sort units of the same row. The search process is based on identifying zeroes in the distance bit signals, from the MSB's to the LSB's. As a zero is found in a row, all the columns with a one in that row are excluded from the subsequent row search. The search process continues until only one distance, the minimum distance, remains and is available at the output of the OR circuit. The above described search/sort circuit may further include a latch allowing the aggregate circuit to sort remaining distances in increasing order.

摘要翻译： 在N个神经元电路的神经网络中，在输入向量和原型向量之间具有被约束的神经元计算的p位宽的距离并存储在其权重存储器中，N个接收的神经元的搜索/ 排序电路。 聚合搜索/分类电路确定计算出的距离之间的最小距离。 每个搜索/分类电路（502-1）具有串联连接的p个基本搜索/分类单元以形成列，使得聚合电路是基本搜索/分类单元的矩阵。 相同位等级的距离位信号被应用于每行的搜索/排序单元。 通过在或门（12.1）中对来自同一行的基本搜索/排序单元的所有本地搜索/排序输出信号进行“或”生成反馈信号。 搜索过程基于识别距离位信号中的零，从MSB到LSB。 由于在一行中找到零，所以在该行中具有一个列的列将从后续行搜索中排除。 搜索过程继续，直到只有一个距离，最小距离保持，并且在OR电路的输出端可用。 上述搜索/分类电路还可以包括允许聚合电路以增加的顺序对剩余距离进行排序的锁存器。

公开(公告)号：US5621863A

公开(公告)日：1997-04-15

申请号：US481591

申请日：1995-06-07

申请人： Jean-Yves Boulet ,  Didier Louis ,  Catherine Godefroy ,  Andre Steimle ,  Pascal Tannhof ,  Guy Paillet

发明人： Jean-Yves Boulet ,  Didier Louis ,  Catherine Godefroy ,  Andre Steimle ,  Pascal Tannhof ,  Guy Paillet

IPC分类号： G06F15/18 ,  G06K9/66 ,  G06N3/00 ,  G06N3/06 ,  G06N3/063 ,  G06N3/08

CPC分类号： G06K9/6272 ,  G06K9/00986 ,  G06N3/063

摘要： In a neural network comprised of a plurality of neuron circuits, an improved neuron circuit that generates local result signals, e.g. of the fire type, and a local output signal of the distance or category type. The neuron circuit which is connected to buses that transport input data (e.g. the input category) and control signals. A multi-norm distance evaluation circuit calculates the distance D between the input vector and a prototype vector stored in a R/W memory circuit. A distance compare circuit compares this distance D with either the stored prototype vector's actual influence field or the lower limit thereof to generate first and second comparison signals. An identification circuit processes the comparison signals, the input category signal, the local category signal and a feedback signal to generate local result signals that represent the neuron circuit's response to the input vector. A minimum distance determination circuit determines the minimum distance Dmin among all the calculated distances from all of the neuron circuits of the neural network and generates a local output signal of the distance type. The circuit may be used to search and sort categories. The feed-back signal is collectively generated by all the neuron circuits by ORing all the local distances/categories. A daisy chain circuit is serially connected to corresponding daisy chain circuits of two adjacent neuron circuits to chain the neurons together. The daisy chain circuit also determines the neuron circuit state as free or engaged. Finally, a context circuitry enables or inhibits neuron participation with other neuron circuits in generation of the feedback signal.

摘要翻译： 在由多个神经元电路组成的神经网络中，生成本地结果信号的改进的神经元电路，例如， 的火灾类型，以及距离或类别类型的本地输出信号。 连接到传送输入数据（例如输入类别）和控制信号的总线的神经元电路。 多范围距离评估电路计算输入矢量和存储在R / W存储器电路中的原型矢量之间的距离D. 距离比较电路将该距离D与存储的原型矢量的实际影响场或其下限进行比较，以产生第一和第二比较信号。 识别电路处理比较信号，输入类别信号，局部类别信号和反馈信号，以产生表示神经元电路对输入矢量的响应的本地结果信号。 最小距离确定电路确定来自神经网络的所有神经元电路的所有计算距离中的最小距离Dmin，并产生距离类型的局部输出信号。 该电路可用于搜索和分类。 所有的神经元电路通过对所有的局部距离/类别进行OR运算来共同地产生反馈信号。 菊花链电路串联连接到两个相邻神经元电路的相应菊花链电路，以将神经元链接在一起。 菊花链电路还将神经元电路状态确定为自由或接合。 最后，上下文电路在反馈信号的产生中实现或抑制与其他神经元电路的神经元参与。

公开(公告)号：US5717832A

公开(公告)日：1998-02-10

申请号：US488443

申请日：1995-06-07

申请人： Andre Steimle ,  Pascal Tannhof ,  Guy Paillet

发明人： Andre Steimle ,  Pascal Tannhof ,  Guy Paillet

IPC分类号： G06F15/18 ,  G06N3/00 ,  G06N3/04 ,  G06N3/06 ,  G06N3/063 ,  G06E1/00

CPC分类号： G06K9/00986 ,  G06K9/6271 ,  G06N3/063

摘要： A base neural semiconductor chip (10) including a neural network or unit (11(#)). The neural network (11(#)) has a plurality of neuron circuits fed by different buses transporting data such as the input vector data, set-up parameters, and control signals. Each neuron circuit (11) includes logic for generating local result signals of the "fire" type (F) and a local output signal (NOUT) of the distance or category type on respective buses (NR-BUS, NOUT-BUS). An OR circuit (12) performs an OR function for all corresponding local result and output signals to generate respective first global result (R*) and output (OUT*) signals on respective buses (R*-BUS, OUT*-BUS) that are merged in an on-chip common communication bus (COM*-BUS) shared by all neuron circuits of the chip. In a multi-chip network, an additional OR function is performed between all corresponding first global result and output signals (which are intermediate signals) to generate second global result (R**) and output (OUT**) signals, preferably by dotting onto an off-chip common communication bus (COM**-BUS) in the chip's driver block (19). This latter bus is shared by all the base neural network chips that are connected to it in order to incorporate a neural network of the desired size. In the chip, a multiplexer (21) may select either the intermediate output or the global output signal to be fed back to all neuron circuits of the neural network, depending on whether the chip is used in a single or multi-chip environment via a feed-back bus (OR-BUS). The feedback signal is the result of a collective processing of all the local output signals.

摘要翻译： 一种包括神经网络或单元（11（＃））的基本神经半导体芯片（10）。 神经网络（11（＃））具有由不同总线馈送的多个神经元电路，其传送诸如输入矢量数据，设置参数和控制信号的数据。 每个神经元电路（11）包括用于在相应总线（NR-BUS，NOUT-BUS）上产生“火”类型（F）的本地结果信号和距离或类别类型的本地输出信号（NOUT）的逻辑。 OR电路（12）对所有对应的本地结果和输出信号执行OR功能，以在相应总线（R * -BUS，OUT * -BUS）上产生相应的第一全局结果（R *）和输出（OUT *）信号， 被合并在由芯片的所有神经元电路共享的片上公共通信总线（COM * -BUS）中。 在多芯片网络中，在所有对应的第一全局结果和输出信号（它们是中间信号）之间执行附加OR功能，以产生第二全局结果（R **）和输出（OUT **）信号，优选地通过点划线 在芯片的驱动器块（19）中的片外公共通信总线（COM ** - BUS）上。 该后一个总线由连接到它的所有基本神经网络芯片共享以便并入所需大小的神经网络。 在芯片中，多路复用器（21）可以选择要反馈给神经网络的所有神经元电路的中间输出或全局输出信号，这取决于芯片是经由单芯片还是多芯片环境使用 反馈总线（OR-BUS）。 反馈信号是对所有局部输出信号的集中处理的结果。

公开(公告)号：US5710869A

公开(公告)日：1998-01-20

申请号：US485337

申请日：1995-06-07

申请人： Catherine Godefroy ,  Andre Steimle ,  Pascal Tannhof ,  Guy Paillet

发明人： Catherine Godefroy ,  Andre Steimle ,  Pascal Tannhof ,  Guy Paillet

IPC分类号： G06F15/18 ,  G06N3/00 ,  G06N3/04 ,  G06N3/06 ,  G06N3/063 ,  G06F15/00

CPC分类号： G06N3/063

摘要： Each daisy chain circuit is serially connected to the two adjacent neuron circuits, so that all the neuron circuits form a chain. The daisy chain circuit distinguishes between the two possible states of the neuron circuit (engaged or free) and identifies the first free "or ready to learn" neuron circuit in the chain, based on the respective values of the input (DCI) and output (DCO) signals of the daisy chain circuit. The ready to learn neuron circuit is the only neuron circuit of the neural network having daisy chain input and output signals complementary to each other. The daisy chain circuit includes a 1-bit register (601) controlled by a store enable signal (ST) which is active at initialization or, during the learning phase when a new neuron circuit is engaged. At initialization, all the Daisy registers of the chain are forced to a first logic value. The DCI input of the first daisy chain circuit in the chain is connected to a second logic value, such that after initialization, it is the ready to learn neuron circuit. In the learning phase, the ready to learn neuron's 1-bit daisy register contents are set to the second logic value by the store enable signal, it is said "engaged". As neurons are engaged, each subsequent neuron circuit in the chain then becomes the next ready to learn neuron circuit.

摘要翻译： 每个菊花链电路串联连接到两个相邻的神经元电路，使得所有的神经元电路形成链。 菊花链电路基于输入（DCI）和输出（DCI）的相应值来区分神经元电路的两种可能状态（被接合或自由）并且识别链中的第一个“准备学习”神经元电路 DCO）信号。 准备学习神经元电路是具有菊花链输入和输出信号彼此互补的神经网络的唯一神经元电路。 菊花链电路包括由初始化时有效的存储使能信号（ST）控制的1位寄存器（601），或者在新的神经元电路被接合时的学习阶段。 在初始化时，链的所有Daisy寄存器都被强制为第一个逻辑值。 链中第一个菊花链电路的DCI输入连接到第二个逻辑值，这样在初始化之后就可以学习神经元电路了。 在学习阶段，准备学习神经元的1位菊花寄存器内容通过存储使能信号设置为第二个逻辑值，它被称为“被接合”。 随着神经元的啮合，链中随后的每个神经元电路就成为下一个准备学习神经元电路的准备。