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公开(公告)号：US07870347B2
公开(公告)日：2011-01-11
申请号：US10570236
申请日：2004-08-19
CPC分类号： G06F13/1663 , G06F12/0831
摘要： The disclosed data processing system comprises a memory means (SDRAM), a plurality of data processing means (IP) provided for accessing to said memory means (SDRAM), and a communication interface means coupled between said memory means (SDRAM) and said plurality of data processing means (IP), said communication interface means including a network of nodes (H 11, H 12, H2), each node comprising at least one slave port (s) for receiving a memory access request from a data processing means (IP) or from a previous node and at least one master port (m) for issuing a memory access request to a next node or to said memory means (SDRAM) in accordance with the memory access request received at said slave port (s), wherein said at least one slave port (s) is connected to a master port (m) of a previous node or to one of said data processing means (IP) and said at least one master port (m) is connected to a slave port (s) of a next node or to said memory means (SDRAM).
摘要翻译： 所公开的数据处理系统包括存储装置（SDRAM），提供用于访问所述存储装置（SDRAM）的多个数据处理装置（IP），以及耦合在所述存储装置（SDRAM）和所述多个 数据处理装置（IP），所述通信接口装置包括节点网络（H 11，H 12，H 2），每个节点包括用于从数据处理装置（IP）接收存储器访问请求的至少一个从端口 ）或来自前一节点的至少一个主端口（m），用于根据在所述从端口处接收到的存储器访问请求向下一个节点或所述存储器装置（SDRAM）发出存储器访问请求， 所述至少一个从属端口连接到先前节点的主端口（m）或所述数据处理装置（IP）中的一个，并且所述至少一个主端口（m）连接到从端口 s）或所述存储装置（SDRAM）。
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公开(公告)号：US20070028038A1
公开(公告)日：2007-02-01
申请号：US10570236
申请日：2004-08-19
IPC分类号： G06F12/00
CPC分类号： G06F13/1663 , G06F12/0831
摘要： The disclosed data processing system comprises a memory means (SDRAM), a plurality of data processing means (IP) provided for accessing to said memory means (SDRAM), and a communication interface means coupled between said memory means (SDRAM) and said plurality of data processing means (IP), said communication interface means including a network of nodes (H 11, H 12, H2), each node comprising at least one slave port (s) for receiving a memory access request from a data processing means (IP) or from a previous node and at least one master port (m) for issuing a memory access request to a next node or to said memory means (SDRAM) in accordance with the memory access request received at said slave port (s), wherein said at least one slave port (s) is connected to a master port (m) of a previous node or to one of said data processing means (IP) and said at least one master port (m) is connected to a slave port (s) of a next node or to said memory means (SDRAM).
摘要翻译： 所公开的数据处理系统包括存储装置（SDRAM），提供用于访问所述存储装置（SDRAM）的多个数据处理装置（IP），以及耦合在所述存储装置（SDRAM）和所述多个 数据处理装置（IP），所述通信接口装置包括节点网络（H 11，H 12，H 2），每个节点包括用于从数据处理装置接收存储器访问请求的至少一个从端口（ IP）或至少一个主端口（m），用于根据在所述从端口处接收到的存储器访问请求向下一个节点或所述存储器装置（SDRAM）发出存储器访问请求， 其中所述至少一个从属端口连接到先前节点的主端口（m）或所述数据处理装置（IP）中的一个，并且所述至少一个主端口（m）连接到从端口 （SDRAM）的一个或多个。
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公开(公告)号：US08745335B2
公开(公告)日：2014-06-03
申请号：US13171484
申请日：2011-06-29
CPC分类号： G06F13/1605 , G06F13/161 , G06F13/18
摘要： Memory arbiter with latency guarantees for multiple ports. A method of controlling access to an electronic memory includes measuring a latency value indicative of a time difference between origination of an access request from a port of a plurality of ports and a response from the electronic memory. The method also includes calculating a difference between the latency value for the port and a target value associated with the port. The method further includes calculating a running sum of differences for the port covering each of a plurality of access requests. Further, the method includes determining a delta of a priority value for the port based on the running sum of differences. Moreover, the method includes prioritizing the access by the plurality of ports according to associated priority values.
摘要翻译： 具有延迟保证的多个端口的内存仲裁器。 控制对电子存储器的访问的方法包括测量表示来自多个端口的接入请求的起始点与来自电子存储器的响应之间的时间差的等待时间值。 该方法还包括计算端口的等待时间值与与端口相关联的目标值之间的差异。 该方法还包括计算覆盖多个访问请求中的每一个的端口的差异的运行总和。 此外，该方法包括基于运行的差异和来确定端口的优先级值的增量。 此外，该方法包括根据相关联的优先级值对多个端口的访问进行优先级排序。
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公开(公告)号：US20130007386A1
公开(公告)日：2013-01-03
申请号：US13171484
申请日：2011-06-29
IPC分类号： G06F12/08
CPC分类号： G06F13/1605 , G06F13/161 , G06F13/18
摘要： Memory arbiter with latency guarantees for multiple ports. A method of controlling access to an electronic memory includes measuring a latency value indicative of a time difference between origination of an access request from a port of a plurality of ports and a response from the electronic memory. The method also includes calculating a difference between the latency value for the port and a target value associated with the port. The method further includes calculating a running sum of differences for the port covering each of a plurality of access requests. Further, the method includes determining a delta of a priority value for the port based on the running sum of differences. Moreover, the method includes prioritizing the access by the plurality of ports according to associated priority values.
摘要翻译： 具有延迟保证的多个端口的内存仲裁器。 控制对电子存储器的访问的方法包括测量表示来自多个端口的接入请求的起始点与来自电子存储器的响应之间的时间差的等待时间值。 该方法还包括计算端口的等待时间值与与端口相关联的目标值之间的差异。 该方法还包括计算覆盖多个访问请求中的每一个的端口的差异的运行总和。 此外，该方法包括基于运行的差异和来确定端口的优先级值的增量。 此外，该方法包括根据相关联的优先级值对多个端口的访问进行优先级排序。
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公开(公告)号：US20100306426A1
公开(公告)日：2010-12-02
申请号：US12599062
申请日：2008-05-14
IPC分类号： G06F5/14
CPC分类号： G06F5/12
摘要： A FIFO memory circuit is for interfacing between circuits with different clock domains. The circuit has a FIFO memory (10), a write pointer circuit (16) clocked by the clock of a first clock domain and controlling the memory location to which data is written, and a read pointer circuit clocked by the clock of a second clock domain and controlling the memory location from which data is read. The read and write pointer circuits use gray coding. The memory circuit further comprises a duplicate write pointer circuit (30) which has its write pointer address incremented synchronously with the write pointer circuit (16), and which has a starting write address selected such that the duplicate write pointer address lags behind the write pointer address circuit by a number of address locations corresponding to the size of the FIFO memory (10). A comparator (34) compares the read pointer circuit address with the duplicate write pointer circuit address for determining a full status of the FIFO memory.
摘要翻译： FIFO存储器电路用于在具有不同时钟域的电路之间进行接口。 电路具有FIFO存储器（10），由第一时钟域的时钟定时并且控制写入数据的存储器位置的写指针电路（16）以及由第二时钟的时钟脉冲定时的读指针电路 并控制读取数据的存储器位置。 读写指针电路采用灰度编码。 存储器电路还包括一个重写写指针电路（30），它具有与写指针电路（16）同步增加的写指针地址，并且具有选择的开始写地址，使得重写写指针地址落在写指针后面 地址电路由与FIFO存储器（10）的大小对应的多个地址位置。 比较器（34）将读取指针电路地址与用于确定FIFO存储器的完整状态的重复写指针电路地址进行比较。
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公开(公告)号：US20110116557A1
公开(公告)日：2011-05-19
申请号：US12876782
申请日：2010-09-07
IPC分类号： H04L27/00
CPC分类号： H04L7/0331 , G06F13/385 , H04L7/0087 , H04L7/044
摘要： A universal asynchronous receiver-transmitter module that includes a sampling controller that assigns a variable number of active edges in a clock signal to respective bits in a serial data signal. A serial data reception path derives a bit from the serial data signal on the basis of the variable number of active edges that the sampling controller has assigned to the bit.
摘要翻译： 通用异步接收机 - 发射机模块，其包括采样控制器，该采样控制器将时钟信号中的可变数量的有效边沿分配给串行数据信号中的相应位。 基于采样控制器分配给该位的有效边沿的可变数量，串行数据接收路径从串行数据信号中得到一位。
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公开(公告)号：US08331427B2
公开(公告)日：2012-12-11
申请号：US12876782
申请日：2010-09-07
IPC分类号： H04B1/38
CPC分类号： H04L7/0331 , G06F13/385 , H04L7/0087 , H04L7/044
摘要： A universal asynchronous receiver-transmitter module that includes a sampling controller that assigns a variable number of active edges in a clock signal to respective bits in a serial data signal. A serial data reception path derives a bit from the serial data signal on the basis of the variable number of active edges that the sampling controller has assigned to the bit.
摘要翻译： 通用异步接收机 - 发射机模块，其包括采样控制器，该采样控制器将时钟信号中的可变数量的有效边沿分配给串行数据信号中的相应位。 基于采样控制器分配给该位的有效边沿的可变数量，串行数据接收路径从串行数据信号中得到一位。
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公开(公告)号：US08612651B2
公开(公告)日：2013-12-17
申请号：US12599062
申请日：2008-05-14
CPC分类号： G06F5/12
摘要： A FIFO memory circuit is for interfacing between circuits with different clock domains. The circuit has a FIFO memory (10), a write pointer circuit (16) clocked by the clock of a first clock domain and controlling the memory location to which data is written, and a read pointer circuit clocked by the clock of a second clock domain and controlling the memory location from which data is read. The read and write pointer circuits use gray coding. The memory circuit further comprises a duplicate write pointer circuit (30) which has its write pointer address incremented synchronously with the write pointer circuit (16), and which has a starting write address selected such that the duplicate write pointer address lags behind the write pointer address circuit by a number of address locations corresponding to the size of the FIFO memory (10). A comparator (34) compares the read pointer circuit address with the duplicate write pointer circuit address for determining a full status of the FIFO memory.
摘要翻译： FIFO存储器电路用于在具有不同时钟域的电路之间进行接口。 电路具有FIFO存储器（10），由第一时钟域的时钟定时并且控制写入数据的存储器位置的写指针电路（16）以及由第二时钟的时钟脉冲定时的读指针电路 并控制读取数据的存储器位置。 读写指针电路采用灰度编码。 存储电路还包括一个重写写指针电路（30），它具有与写指针电路（16）同步增加的写指针地址，并且具有选择的开始写地址，使得重写写指针地址落在写指针之后 地址电路由与FIFO存储器（10）的大小对应的多个地址位置。 比较器（34）将读取指针电路地址与用于确定FIFO存储器的完整状态的重复写指针电路地址进行比较。
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