利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

26 条记录 (耗时 0.024 秒)

    System and method for prefetching data from a main computer memory into a cache memory
    1.
    发明授权
    System and method for prefetching data from a main computer memory into a cache memory 失效
    将数据从主计算机存储器预取到高速缓冲存储器的系统和方法

    公开(公告)号：US5530941A

    公开(公告)日：1996-06-25

    申请号：US563215

    申请日：1990-08-06

    申请人： Pirmin L. Weisser ,  Fulps V. Vermeer ,  Edward C. King

    发明人： Pirmin L. Weisser ,  Fulps V. Vermeer ,  Edward C. King

    IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F13/28

    CPC分类号： G06F9/3802 ,  G06F12/0862 ,  G06F2212/6022

    摘要： A method and system for transferring data elements from a computer main memory to a cache memory. The main and cache memories are accessible by a host processor and other bus masters connected thereto by a bus. Code data elements to be read by the host processor are predicted. The predicted code data elements are then transferred from the main memory to cache memory without delaying memory access requests for data from the other bus masters.

    摘要翻译： 一种用于将数据元素从计算机主存储器传送到高速缓冲存储器的方法和系统。 主存储器和高速缓冲存储器可由主机处理器和通过总线与其连接的其它总线主机访问。 预测要由主处理器读取的代码数据元素。 然后将预测的代码数据元素从主存储器传送到高速缓冲存储器，而不会延迟来自其他总线主机的数据的存储器访问请求。

    System and method for interleaving memory addresses between memory banks based on the capacity of the memory banks
    5.
    发明授权
    System and method for interleaving memory addresses between memory banks based on the capacity of the memory banks 失效
    基于存储体的容量对存储体之间的存储器地址进行交织的系统和方法

    公开(公告)号：US5630098A

    公开(公告)日：1997-05-13

    申请号：US752702

    申请日：1991-08-30

    申请人： Fulps V. Vermeer ,  Edward C. King

    发明人： Fulps V. Vermeer ,  Edward C. King

    IPC分类号： G06F12/06

    CPC分类号： G06F12/0607

    摘要： The invention is a system and method for accessing a plurality of memory banks. The system includes a number of memory banks, a register and a controller. The register stores capacity information of each memory bank. The controller is connected to the register and memory banks and uses the capacity information to determine whether or not addresses are to be interleaved between a pair of memory banks. If the memory banks are of similar capacities, the addresses may be interleaved therebetween.

    摘要翻译： 本发明是用于访问多个存储体的系统和方法。 该系统包括多个存储体，寄存器和控制器。 寄存器存储每个存储体的容量信息。 控制器连接到寄存器和存储体，并使用容量信息来确定地址是否要在一对存储体之间交错。 如果存储体具有相似的容量，那么这些地址可以在它们之间交错。

    Computer memory open page bias method and system
    6.
    发明授权
    Computer memory open page bias method and system 失效
    计算机内存打开页面偏置方法和系统

    公开(公告)号：US5604883A

    公开(公告)日：1997-02-18

    申请号：US629789

    申请日：1996-04-09

    申请人： Edward C. King ,  Fulps V. Vermeer

    发明人： Edward C. King ,  Fulps V. Vermeer

    IPC分类号： G06F12/08 ,  G06F12/02 ,  G06F12/06 ,  G06F12/12 ,  G11C7/10

    CPC分类号： G11C7/1021 ,  G06F12/0215

    摘要： A method for accessing data in a computer memory divided into pages. A first page is opened in response to a first address to access data therein. A second page is opened in response to a second address to access data therein. The first page is then reopened prior to receiving another address signal.

    摘要翻译： 一种访问计算机内存中划分为页面的数据的方法。 响应于第一地址来访问其中的数据而打开第一页。 响应于第二地址来访问其中的数据而打开第二页。 然后在接收另一个地址信号之前重新打开第一页。

    Memory system with write buffer, prefetch and internal caches
    7.
    发明授权
    Memory system with write buffer, prefetch and internal caches 失效
    具有写入缓冲区，预取和内部缓存的内存系统

    公开(公告)号：US5835945A

    公开(公告)日：1998-11-10

    申请号：US563216

    申请日：1990-08-06

    申请人： Edward C. King ,  Jackson L. Ellis ,  Robert B. Moussavi ,  Pirmin L. Weisser

    发明人： Edward C. King ,  Jackson L. Ellis ,  Robert B. Moussavi ,  Pirmin L. Weisser

    IPC分类号： G06F12/08

    CPC分类号： G06F12/084

    摘要： A statistically fast, high performance computer memory system including a system memory for storing code and non-code data accessible by at least two bus masters, a bus connecting the memory with the bus masters, and a plurality of caches connected to the bus. An internal cache holds data selected solely on the basis of memory accesses by the host processor, a pre-fetch cache pre-fetches code from the memory, and a write buffer cache connected to the bus for buffering data written to the memory.

    摘要翻译： 统计上快速的高性能计算机存储器系统，包括用于存储可由至少两个总线主机访问的代码和非代码数据的系统存储器，连接存储器与总线主机的总线，以及连接到总线的多个高速缓存。 内部缓存保存仅基于主处理器的存储器访问选择的数据，预取缓存从存储器预取代码，以及连接到总线的写入缓冲器高速缓存，用于缓冲写入存储器的数据。

    Method and apparatus for interactively displaying signal information during computer simulation of an electrical circuit
    8.
    发明授权
    Method and apparatus for interactively displaying signal information during computer simulation of an electrical circuit 失效
    用于在电路的计算机模拟期间交互地显示信号信息的方法和装置

    公开(公告)号：US5852564A

    公开(公告)日：1998-12-22

    申请号：US752498

    申请日：1996-11-20

    申请人： Edward C. King ,  Alan G. Smith

    发明人： Edward C. King ,  Alan G. Smith

    IPC分类号： G06F11/26 ,  G06F17/50 ,  G06F9/455

    CPC分类号： G06F17/5022 ,  G06F11/261

    摘要： A computer system simulator concurrently models both processor operation and signal logic behavior and provides a high degree of user interaction and flexibility in the observation and control of signal values and memory contents during the execution of a simulation. During simulation, source equations for signals can be requested for display either through direct input of a signal name or through graphical interface with the simulation display. Signal equations can in this manner be traced back through several levels, which conveniently provides important information during the observation and modification of signal values. Memory areas may be associated with a processor and loaded with data to be executed by that processor during the simulation. The data can be displayed in both numerical and assembly code mnemonic form, and may also be modified by entering numbers or assembly instructions. The simulated processor execution may thus be interactively modified during the simulation. Additionally, the ability to step the simulation backwards through time, and then forward again, is provided.

    摘要翻译： 计算机系统模拟器同时模拟处理器操作和信号逻辑行为，并且在模拟执行期间在观察和控制信号值和存储器内容方面提供高度的用户交互和灵活性。 在仿真期间，可以通过直接输入信号名称或通过模拟显示的图形界面来请求信号的源方程式进行显示。 信号方程可以以这种方式追溯到几个级别，这在信号值的观察和修改期间便于提供重要的信息。 存储器区域可以与处理器相关联，并且在仿真期间加载要由该处理器执行的数据。 数据可以以数字和汇编代码助记符形式显示，也可以通过输入数字或汇编指令进行修改。 因此可以在模拟期间交互地修改模拟的处理器执行。 此外，还提供了通过时间向后延伸模拟，然后再次转发的能力。

    Method and apparatus for interactively displaying signal information during computer simulation of an electrical circuit
    9.
    发明授权
    Method and apparatus for interactively displaying signal information during computer simulation of an electrical circuit 失效
    用于在电路的计算机模拟期间交互地显示信号信息的方法和装置

    公开(公告)号：US5615356A

    公开(公告)日：1997-03-25

    申请号：US334769

    申请日：1994-11-04

    申请人： Edward C. King ,  Alan G. Smith

    发明人： Edward C. King ,  Alan G. Smith

    IPC分类号： G06F11/26 ,  G06F17/50 ,  G06F15/60

    CPC分类号： G06F17/5022 ,  G06F11/261

    摘要： A computer system simulator concurrently models both processor operation and signal logic behavior and provides a high degree of user interaction and flexibility in the observation and control of signal values and memory contents during the execution of a simulation. During simulation, source equations for signals can be requested for display either through direct input of a signal name or through graphical interface with the simulation display. Signal equations can in this manner be traced back through several levels, which conveniently provides important information during the observation and modification of signal values. Memory areas may be associated with a processor and loaded with data to be executed by that processor during the simulation. The data can be displayed in both numerical and assembly code mnemonic form, and may also be modified by entering numbers or assembly instructions. The simulated processor execution may thus be interactively modified during the simulation. Additionally, the ability to step the simulation backwards through time, and then forward again, is provided.

    摘要翻译： 计算机系统模拟器同时模拟处理器操作和信号逻辑行为，并且在模拟执行期间在观察和控制信号值和存储器内容方面提供高度的用户交互和灵活性。 在仿真期间，可以通过直接输入信号名称或通过模拟显示的图形界面来请求信号的源方程式进行显示。 信号方程可以以这种方式追溯到几个级别，这在信号值的观察和修改期间便于提供重要的信息。 存储器区域可以与处理器相关联，并且在仿真期间加载要由该处理器执行的数据。 数据可以以数字和汇编代码助记符形式显示，也可以通过输入数字或汇编指令进行修改。 因此可以在模拟期间交互地修改模拟的处理器执行。 此外，还提供了通过时间向后延伸模拟，然后再次转发的能力。

    High speed, direct register access operation for parallel processing units
    10.
    发明授权
    High speed, direct register access operation for parallel processing units 失效
    并行处理单元的高速，直接寄存器访问操作

    公开(公告)号：US5848276A

    公开(公告)日：1998-12-08

    申请号：US554671

    申请日：1995-11-08

    申请人： Edward C. King ,  Alan G. Smith ,  Scott Smith

    发明人： Edward C. King ,  Alan G. Smith ,  Scott Smith

    IPC分类号： G06F9/38 ,  G06F15/80 ,  G06F9/30

    CPC分类号： G06F15/8015 ,  G06F9/3885

    摘要： The present invention provides for a computer system having a plurality of parallel processor units with each processor unit associated with at least one register for receiving data for the processor unit. The computer system has a bus unit, coupled to the output of each processor unit and the associated register of each processor unit, to transfer the output data of a first processor unit into an associated register of a second processor unit in a single computer operation. The second processor unit is prevented from reading the associated register until the bus unit transfers the output data from the first processor unit to the second processor unit.

    摘要翻译： 本发明提供一种具有多个并行处理器单元的计算机系统，每个处理器单元与至少一个用于接收处理器单元的数据的寄存器相关联。 计算机系统具有耦合到每个处理器单元的输出和每个处理器单元的相关联的寄存器的总线单元，以在单个计算机操作中将第一处理器单元的输出数据传送到第二处理器单元的关联寄存器。 第二处理器单元被阻止读取相关联的寄存器，直到总线单元将输出数据从第一处理器单元传送到第二处理器单元。