公开(公告)号：US5848276A

公开(公告)日：1998-12-08

申请号：US554671

申请日：1995-11-08

申请人： Edward C. King ,  Alan G. Smith ,  Scott Smith

发明人： Edward C. King ,  Alan G. Smith ,  Scott Smith

IPC分类号： G06F9/38 ,  G06F15/80 ,  G06F9/30

CPC分类号： G06F15/8015 ,  G06F9/3885

摘要： The present invention provides for a computer system having a plurality of parallel processor units with each processor unit associated with at least one register for receiving data for the processor unit. The computer system has a bus unit, coupled to the output of each processor unit and the associated register of each processor unit, to transfer the output data of a first processor unit into an associated register of a second processor unit in a single computer operation. The second processor unit is prevented from reading the associated register until the bus unit transfers the output data from the first processor unit to the second processor unit.

摘要翻译： 本发明提供一种具有多个并行处理器单元的计算机系统，每个处理器单元与至少一个用于接收处理器单元的数据的寄存器相关联。 计算机系统具有耦合到每个处理器单元的输出和每个处理器单元的相关联的寄存器的总线单元，以在单个计算机操作中将第一处理器单元的输出数据传送到第二处理器单元的关联寄存器。 第二处理器单元被阻止读取相关联的寄存器，直到总线单元将输出数据从第一处理器单元传送到第二处理器单元。

公开(公告)号：US5852564A

公开(公告)日：1998-12-22

申请号：US752498

申请日：1996-11-20

申请人： Edward C. King ,  Alan G. Smith

发明人： Edward C. King ,  Alan G. Smith

IPC分类号： G06F11/26 ,  G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5022 ,  G06F11/261

摘要： A computer system simulator concurrently models both processor operation and signal logic behavior and provides a high degree of user interaction and flexibility in the observation and control of signal values and memory contents during the execution of a simulation. During simulation, source equations for signals can be requested for display either through direct input of a signal name or through graphical interface with the simulation display. Signal equations can in this manner be traced back through several levels, which conveniently provides important information during the observation and modification of signal values. Memory areas may be associated with a processor and loaded with data to be executed by that processor during the simulation. The data can be displayed in both numerical and assembly code mnemonic form, and may also be modified by entering numbers or assembly instructions. The simulated processor execution may thus be interactively modified during the simulation. Additionally, the ability to step the simulation backwards through time, and then forward again, is provided.

摘要翻译： 计算机系统模拟器同时模拟处理器操作和信号逻辑行为，并且在模拟执行期间在观察和控制信号值和存储器内容方面提供高度的用户交互和灵活性。 在仿真期间，可以通过直接输入信号名称或通过模拟显示的图形界面来请求信号的源方程式进行显示。 信号方程可以以这种方式追溯到几个级别，这在信号值的观察和修改期间便于提供重要的信息。 存储器区域可以与处理器相关联，并且在仿真期间加载要由该处理器执行的数据。 数据可以以数字和汇编代码助记符形式显示，也可以通过输入数字或汇编指令进行修改。 因此可以在模拟期间交互地修改模拟的处理器执行。 此外，还提供了通过时间向后延伸模拟，然后再次转发的能力。

公开(公告)号：US5615356A

公开(公告)日：1997-03-25

申请号：US334769

申请日：1994-11-04

申请人： Edward C. King ,  Alan G. Smith

发明人： Edward C. King ,  Alan G. Smith

IPC分类号： G06F11/26 ,  G06F17/50 ,  G06F15/60

CPC分类号： G06F17/5022 ,  G06F11/261

摘要： A computer system simulator concurrently models both processor operation and signal logic behavior and provides a high degree of user interaction and flexibility in the observation and control of signal values and memory contents during the execution of a simulation. During simulation, source equations for signals can be requested for display either through direct input of a signal name or through graphical interface with the simulation display. Signal equations can in this manner be traced back through several levels, which conveniently provides important information during the observation and modification of signal values. Memory areas may be associated with a processor and loaded with data to be executed by that processor during the simulation. The data can be displayed in both numerical and assembly code mnemonic form, and may also be modified by entering numbers or assembly instructions. The simulated processor execution may thus be interactively modified during the simulation. Additionally, the ability to step the simulation backwards through time, and then forward again, is provided.

摘要翻译： 计算机系统模拟器同时模拟处理器操作和信号逻辑行为，并且在模拟执行期间在观察和控制信号值和存储器内容方面提供高度的用户交互和灵活性。 在仿真期间，可以通过直接输入信号名称或通过模拟显示的图形界面来请求信号的源方程式进行显示。 信号方程可以以这种方式追溯到几个级别，这在信号值的观察和修改期间便于提供重要的信息。 存储器区域可以与处理器相关联，并且在仿真期间加载要由该处理器执行的数据。 数据可以以数字和汇编代码助记符形式显示，也可以通过输入数字或汇编指令进行修改。 因此可以在模拟期间交互地修改模拟的处理器执行。 此外，还提供了通过时间向后延伸模拟，然后再次转发的能力。

公开(公告)号：US5761455A

公开(公告)日：1998-06-02

申请号：US384293

申请日：1995-02-06

申请人： Edward C. King ,  Alan G. Smith ,  James C. Lee

发明人： Edward C. King ,  Alan G. Smith ,  James C. Lee

IPC分类号： G06F13/16 ,  G06F13/40 ,  G06F15/173 ,  G06F13/14

CPC分类号： G06F13/1657 ,  G06F13/4022 ,  G06F15/17337

摘要： A parallel processing system is provided with a plurality of processors and a plurality of memories, and bus units with arbitration coupling the processors and memories. A bus unit provides a pathway between one processor and the bus unit's respective memory. Each bus unit arbitrates multiple simultaneous access requests for its respective memory and communicates its decisions to other bus units so that a memory access requiring multiple memories will only occur if all those memories are available. The coupling of processors to memories can change, dynamically, each bus cycle without the need for setup before the bus cycle either by pipelining or having unused bus cycles. In a specific embodiment, the memory access information is provided on high order address lines, where the processor logically accesses different memory address spaces to make different accesses, thereby sharing memory with other processors.

摘要翻译： 并行处理系统具有多个处理器和多个存储器以及具有仲裁耦合处理器和存储器的总线单元。 总线单元提供一个处理器和总线单元的各自存储器之间的通路。 每个总线单元对其各自的存储器仲裁多个同时访问请求，并将其决定传达给其它总线单元，使得仅当所有这些存储器都可用时才需要存储器的存储器访问将仅发生。 处理器与存储器的耦合可以动态地改变每个总线周期，而不需要在总线周期之前通过流水线或具有未使用的总线周期进行设置。 在具体实施例中，存储器访问信息被提供在高阶地址线上，其中处理器逻辑地访问不同的存储器地址空间以进行不同的访问，由此与其他处理器共享存储器。

公开(公告)号：US5832253A

公开(公告)日：1998-11-03

申请号：US163442

申请日：1993-12-06

申请人： Edward C. King ,  Alan G. Smith ,  Mark E. Scheitrum

发明人： Edward C. King ,  Alan G. Smith ,  Mark E. Scheitrum

IPC分类号： G06F13/00

CPC分类号： G06F15/17325

摘要： The present invention provides for a computer system having a plurality of parallel processor units. The processor units are connected in common to a signal line with each processor capable of setting a first signal level on the line and monitoring the line in response to instructions to the processor. This allows each processor unit to be notified of the completion of a parallel operation by other participating processor units upon a second signal level on the signal line. More than one signal lines may be connected between the parallel processor units to provide synchronization of different parallel operations between different processor units.

摘要翻译： 本发明提供一种具有多个并行处理器单元的计算机系统。 处理器单元共同连接到信号线，每个处理器能够设置线路上的第一信号电平并且响应于对处理器的指令来监视线路。 这允许在信号线上的第二信号电平上通知其他参与处理器单元完成并行操作的每个处理器单元。 可以在并行处理器单元之间连接多于一个信号线，以提供不同处理器单元之间的不同并行操作的同步。

公开(公告)号：US5652907A

公开(公告)日：1997-07-29

申请号：US470675

申请日：1995-06-06

申请人： Edward C. King ,  Alan G. Smith

发明人： Edward C. King ,  Alan G. Smith

IPC分类号： G06F9/305 ,  G06F9/38 ,  G06F13/00 ,  G06F15/16

CPC分类号： G06F9/30029 ,  G06F9/3885

摘要： A computer system having a plurality of parallel processor units with each processor unit having an output bus of n bits and an associated mask register is provided. The computer system comprises a bus unit, coupled to the output bus of each processor unit and each associated mask register, for masking the output bus bits with bits in the mask register of each processor unit and logically combining the resulting masked bits from each processor unit into an output bus of n bits in one computer operation.

摘要翻译： 提供具有多个并行处理器单元的计算机系统，每个处理器单元具有n位输出总线和相关联的掩码寄存器。 计算机系统包括耦合到每个处理器单元的输出总线和每个相关联的掩模寄存器的总线单元，用于利用每个处理器单元的屏蔽寄存器中的位来屏蔽输出总线位，并且逻辑地组合来自每个处理器单元的所得到的屏蔽位 在一个计算机操作中成为n位的输出总线。

公开(公告)号：US5499376A

公开(公告)日：1996-03-12

申请号：US163460

申请日：1993-12-06

申请人： Edward C. King ,  Alan G. Smith

发明人： Edward C. King ,  Alan G. Smith

IPC分类号： G06F9/305 ,  G06F9/38 ,  G06F13/00 ,  G06F15/16

CPC分类号： G06F9/30029 ,  G06F9/3885

摘要： A computer system having a plurality of parallel processor units with each processor unit having an output bus of n bits and an associated mask register is provided. The computer system comprises a bus unit, coupled to the output bus of each processor unit and each associated mask register, for masking the output bus bits with bits in the mask register of each processor unit and logically combining the resulting masked bits from each processor unit into an output bus of n bits in one computer operation.

摘要翻译： 提供具有多个并行处理器单元的计算机系统，每个处理器单元具有n位输出总线和相关联的掩码寄存器。 计算机系统包括耦合到每个处理器单元的输出总线和每个相关联的掩模寄存器的总线单元，用于利用每个处理器单元的屏蔽寄存器中的位来屏蔽输出总线位，并逻辑地组合来自每个处理器单元的所得到的屏蔽位 在一个计算机操作中成为n位的输出总线。

公开(公告)号：US07630875B2

公开(公告)日：2009-12-08

申请号：US11160430

申请日：2005-06-23

申请人： Edward C. King ,  Alan G. Smith ,  Jeffrey S. Hammond ,  Richard S. Czyzewski

发明人： Edward C. King ,  Alan G. Smith ,  Jeffrey S. Hammond ,  Richard S. Czyzewski

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A simulation of an electronics system which performs a set of operations of interest. A simulated supervisory circuit detects a state in which all the operations have been completed, and also determines the amount of time until the occurrence of the next relevant event. Simulation time is then advanced by that amount of time. This enables simulation time corresponding to an inactive system to be eliminated.

摘要翻译： 执行感兴趣的一组操作的电子系统的模拟。 模拟监控电路检测所有操作已经完成的状态，并且还确定直到发生下一个相关事件的时间量。 仿真时间提前一段时间。 这使得能够消除与非活动系统相对应的模拟时间。

公开(公告)号：US5835945A

公开(公告)日：1998-11-10

申请号：US563216

申请日：1990-08-06

申请人： Edward C. King ,  Jackson L. Ellis ,  Robert B. Moussavi ,  Pirmin L. Weisser

发明人： Edward C. King ,  Jackson L. Ellis ,  Robert B. Moussavi ,  Pirmin L. Weisser

IPC分类号： G06F12/08

CPC分类号： G06F12/084

摘要： A statistically fast, high performance computer memory system including a system memory for storing code and non-code data accessible by at least two bus masters, a bus connecting the memory with the bus masters, and a plurality of caches connected to the bus. An internal cache holds data selected solely on the basis of memory accesses by the host processor, a pre-fetch cache pre-fetches code from the memory, and a write buffer cache connected to the bus for buffering data written to the memory.

摘要翻译： 统计上快速的高性能计算机存储器系统，包括用于存储可由至少两个总线主机访问的代码和非代码数据的系统存储器，连接存储器与总线主机的总线，以及连接到总线的多个高速缓存。 内部缓存保存仅基于主处理器的存储器访问选择的数据，预取缓存从存储器预取代码，以及连接到总线的写入缓冲器高速缓存，用于缓冲写入存储器的数据。

公开(公告)号：US5530941A

公开(公告)日：1996-06-25

申请号：US563215

申请日：1990-08-06

申请人： Pirmin L. Weisser ,  Fulps V. Vermeer ,  Edward C. King

发明人： Pirmin L. Weisser ,  Fulps V. Vermeer ,  Edward C. King

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F13/28

CPC分类号： G06F9/3802 ,  G06F12/0862 ,  G06F2212/6022

摘要： A method and system for transferring data elements from a computer main memory to a cache memory. The main and cache memories are accessible by a host processor and other bus masters connected thereto by a bus. Code data elements to be read by the host processor are predicted. The predicted code data elements are then transferred from the main memory to cache memory without delaying memory access requests for data from the other bus masters.

摘要翻译： 一种用于将数据元素从计算机主存储器传送到高速缓冲存储器的方法和系统。 主存储器和高速缓冲存储器可由主机处理器和通过总线与其连接的其它总线主机访问。 预测要由主处理器读取的代码数据元素。 然后将预测的代码数据元素从主存储器传送到高速缓冲存储器，而不会延迟来自其他总线主机的数据的存储器访问请求。