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    System and method for intelligent software-controlled cache injection
    1.
    发明授权
    System and method for intelligent software-controlled cache injection 失效
    用于智能软件控制缓存注入的系统和方法

    公开(公告)号：US07774554B2

    公开(公告)日：2010-08-10

    申请号：US11676745

    申请日：2007-02-20

    申请人： Piyush Chaudhary ,  Rama K. Govindaraju ,  Jay Robert Herring ,  Peter Hochschild ,  Chulho Kim ,  Rajeev Sivaram ,  Hanhong Xue

    发明人： Piyush Chaudhary ,  Rama K. Govindaraju ,  Jay Robert Herring ,  Peter Hochschild ,  Chulho Kim ,  Rajeev Sivaram ,  Hanhong Xue

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0862 ,  G06F12/0817

    摘要： A system and method to provide injection of important data directly into a processor's cache location when that processor has previously indicated interest in the data. The memory subsystem at a target processor will determine if the memory address of data to be written to a memory location associated with the target processor is found in a processor cache of the target processor. If it is determined that the memory address is found in a target processor's cache, the data will be directly written to that cache at the same time that the data is being provided to a location in main memory.

    摘要翻译： 当处理器先前已经对数据感兴趣时，提供将重要数据直接注入处理器的高速缓存位置的系统和方法。 目标处理器上的存储器子系统将确定是否在目标处理器的处理器高速缓存中找到要写入到与目标处理器相关联的存储器位置的数据的存储器地址。 如果确定在目标处理器的高速缓存中找到存储器地址，则在将数据提供给主存储器中的位置的同时，数据将被直接写入该高速缓存。

    System and Method for Intelligent Software-Controlled Cache Injection
    2.
    发明申请
    System and Method for Intelligent Software-Controlled Cache Injection 失效
    智能软件控制缓存注入系统与方法

    公开(公告)号：US20080201532A1

    公开(公告)日：2008-08-21

    申请号：US11676745

    申请日：2007-02-20

    申请人： Piyush Chaudhary ,  Rama K. Govindaraju ,  Jay Robert Herring ,  Peter Hochschild ,  Chulho Kim ,  Rajeev Sivaram ,  Hanhong Xue

    发明人： Piyush Chaudhary ,  Rama K. Govindaraju ,  Jay Robert Herring ,  Peter Hochschild ,  Chulho Kim ,  Rajeev Sivaram ,  Hanhong Xue

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0862 ,  G06F12/0817

    摘要： A system and method to provide injection of important data directly into a processor's cache location when that processor has previously indicated interest in the data. The memory subsystem at a target processor will determine if the memory address of data to be written to a memory location associated with the target processor is found in a processor cache of the target processor. If it is determined that the memory address is found in a target processor's cache, the data will be directly written to that cache at the same time that the data is being provided to a location in main memory.

    摘要翻译： 当处理器先前已经对数据感兴趣时，提供将重要数据直接注入处理器的高速缓存位置的系统和方法。 目标处理器上的存储器子系统将确定是否在目标处理器的处理器高速缓存中找到要写入到与目标处理器相关联的存储器位置的数据的存储器地址。 如果确定在目标处理器的高速缓存中找到存储器地址，则在将数据提供给主存储器中的位置的同时，数据将被直接写入该高速缓存。

    Snapshot interface operations
    9.
    发明授权
    Snapshot interface operations 失效
    快照界面操作

    公开(公告)号：US08364849B2

    公开(公告)日：2013-01-29

    申请号：US11017332

    申请日：2004-12-20

    申请人： Piyush Chaudhary ,  Jason E. Goscinski ,  Rama K. Govindaraju ,  Leonard W. Helmer, Jr. ,  Peter H. Hochschild ,  Deryck X. Hong ,  John S. Houston ,  Jang-Soo Lee ,  Steven J. Martin ,  Yuqing Zhu

    发明人： Piyush Chaudhary ,  Jason E. Goscinski ,  Rama K. Govindaraju ,  Leonard W. Helmer, Jr. ,  Peter H. Hochschild ,  Deryck X. Hong ,  John S. Houston ,  Jang-Soo Lee ,  Steven J. Martin ,  Yuqing Zhu

    IPC分类号： G06F15/16

    CPC分类号： H04L67/1097

    摘要： In a multinode data processing system in which the nodes communicate with one another via communication adapters over a network or switch, the adapters are provided with a dual register mechanism for tracking microcode task status. Upon the issuance of a disruptive command that requires attention from one of the nodes, the task status maintained in one register is copied to the snapshot register. As tasks within the adapter are completed, both registers are updated, thus providing a mechanism for the nodes to determine that all tasks active at the time of the disruptive command have completed. This means that the nodes now have a mechanism for determining, as soon as possible, that all tasks that are active when a disruptive command occurs have completed, thus allowing the data processing node to perform such operations as releasing system memory that is associated with the disruptive command, thus eliminating temporal overhead that can affect performance.

    摘要翻译： 在其中节点通过网络或交换机经由通信适配器彼此通信的多节点数据处理系统中，适配器被提供有用于跟踪微代码任务状态的双重注册机制。 在发出需要从其中一个节点注意的破坏性命令时，将一个寄存器中维护的任务状态复制到快照寄存器。 当适配器中的任务完成时，两个寄存器都被更新，从而为节点确定在破坏性命令时激活的所有任务完成的机制。 这意味着节点现在具有用于尽可能快地确定在发生破坏性命令时活动的所有任务已经完成的机制，从而允许数据处理节点执行诸如释放与 破坏性命令，从而消除可能影响性能的时间开销。