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公开(公告)号:US20240135993A1
公开(公告)日:2024-04-25
申请号:US18492625
申请日:2023-10-22
Applicant: Fu-Chang Hsu
Inventor: Fu-Chang Hsu
CPC classification number: G11C16/0483 , H10B41/10 , H10B41/20 , H10B41/35 , H10B43/10 , H10B43/20 , H10B43/35
Abstract: Various 3D array structures and processes are disclosed. In an embodiment, a word line staircase structure is provided that includes a plurality of word line layers alternately deposited with a plurality of insulating layers to form a stack and a first word line stairstep that includes all the layers of the stack. The staircase structure also includes one or more additional word line stairsteps such that each successive additional word line stairstep is formed to include less layers of the stack than the preceding word line stairstep to form the word line staircase structure. The stairstep structure also includes multiple contact holes formed in each word line stairstep to contact multiple word line layers within that word line stairstep.
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公开(公告)号:US20240130249A1
公开(公告)日:2024-04-18
申请号:US18365936
申请日:2023-08-04
Applicant: Fu-Chang HSU , Kevin HSU
Inventor: Fu-Chang HSU , Kevin HSU
CPC classification number: H10N60/11 , G06N10/00 , H03K3/38 , H10N60/128 , H10N69/00
Abstract: A quantum bit array is disclosed. In an embodiment, the quantum bit array includes a control gate coupled to a qubit and at least one pass gate coupled between the qubit and an adjacent qubit to control operation of the qubit of the quantum bit array, a bit line, and a first transistor channel that connects the bit line to the control gate. The array further comprises at least one word line coupled to the first transistor channel. The at least one word line selectively controls charge flow through the first transistor channel. The array further comprises a capacitor coupled to selectively store charge in the first transistor channel.
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公开(公告)号:US20230154847A1
公开(公告)日:2023-05-18
申请号:US18055397
申请日:2022-11-14
Applicant: Fu-Chang Hsu
Inventor: Fu-Chang Hsu
IPC: H01L23/528 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/775 , H01L21/683 , H01L21/822 , H01L21/8238 , H01L29/66
CPC classification number: H01L23/5286 , H01L27/0922 , H01L29/0673 , H01L29/42392 , H01L29/775 , H01L21/6835 , H01L21/8221 , H01L21/823871 , H01L29/66439 , H01L2221/68372
Abstract: Advanced structures having MOSFET transistors and metal layers are disclosed. In one embodiment, a transistor structure is provided that includes a first transistor layer, a second transistor layer located under the first transistor layer, a first power bus layer located above the first transistor layer, a second power bus layer located under the second transistor layer, and a first interconnect layer located above the first power bus layer.
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公开(公告)号:US20220037519A1
公开(公告)日:2022-02-03
申请号:US17389241
申请日:2021-07-29
Applicant: Fu-Chang Hsu
Inventor: Fu-Chang Hsu
Abstract: Transistor structures and associated processes are disclosed. In an exemplary embodiment, a transistor structure is provided that includes a conductor layer divided into a plurality of separate conductor regions and a plurality of lateral transistors formed on top of the plurality of separate conductor regions, respectively. Each lateral transistor comprises a source, a drain, and a gate region, and at least one of the source, drain, and gate regions of each lateral transistor is conductively coupled underneath to its respective conductor region.
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公开(公告)号:US20210296556A1
公开(公告)日:2021-09-23
申请号:US17209107
申请日:2021-03-22
Applicant: Fu-Chang Hsu , Kevin Hsu
Inventor: Fu-Chang Hsu , Kevin Hsu
Abstract: A quantum bit array is disclosed. In an embodiment, the quantum bit array includes a control gate coupled to a qubit and at least one pass gate coupled between the qubit and an adjacent qubit to control operation of the qubit of the quantum bit array, a bit line, and a first transistor channel that connects the bit line to the control gate. The array further comprises at least one word line coupled to the first transistor channel. The at least one word line selectively controls charge flow through the first transistor channel. The array further comprises a capacitor coupled to selectively store charge in the first transistor channel.
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公开(公告)号:US10557141B2
公开(公告)日:2020-02-11
申请号:US14234007
申请日:2012-07-20
Applicant: Yin-Fu Chang , Aparna Sri Vanguri , Leslie Grist , Holly Tuttle , Hai Ping Hong , Paula Olhoft
Inventor: Yin-Fu Chang , Aparna Sri Vanguri , Leslie Grist , Holly Tuttle , Hai Ping Hong , Paula Olhoft
IPC: C12N15/82
Abstract: The present invention relates to an improved method of producing a transgenic plant. Said method comprises, inter alia, the steps of a) providing a wounded transformable explant comprising a hypocotyl or a portion thereof, at least one cotyledon and wounded tissue, b) transforming cells comprised by said explant, and c) transferring said explant to a growing medium, comprising at least one selection compound for a selectable marker, by inserting the hypocotyl of said explant into said growing medium. Moreover, the present invention relates to a plant obtainable by the method according to the present invention.
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公开(公告)号:US20190108437A1
公开(公告)日:2019-04-11
申请号:US16006730
申请日:2018-06-12
Applicant: Fu-Chang Hsu , Kevin Hsu
Inventor: Fu-Chang Hsu , Kevin Hsu
Abstract: Two and three-dimensional neural network arrays. In an exemplary embodiment, a two-dimensional (2D) neural network array includes a plurality of input neurons connected to a plurality of input lines, and a plurality of output neurons connected to a plurality of output lines. The 2D neural network array also includes synapse elements connected between the input lines and the output lines. Each synapse element includes a programmable resistive element. A three-dimensional (3D) neural network array includes a plurality of stacked two-dimensional (2D) neural network arrays each having a plurality of input neurons connected to a plurality of input layers and a plurality of output neurons connected to a plurality of output layers. The output layers intersect with the input layers and include synapse elements formed between intersecting regions of the input layers and the output layers. Each synapse element includes a programmable resistive element.
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公开(公告)号:US20180165573A1
公开(公告)日:2018-06-14
申请号:US15835375
申请日:2017-12-07
Applicant: Fu-Chang Hsu , Kevin Hsu
Inventor: Fu-Chang Hsu , Kevin Hsu
CPC classification number: G06N3/063 , G06N3/04 , G06N3/0454
Abstract: Three-dimensional neural network array. In an exemplary embodiment, a three-dimensional (3D) neural network includes a plurality of input conductors forming a plurality of stacked input layers having a first orientation, and at least one output conductor forming an output layer having the first orientation. The three-dimensional (3D) neural network also includes a plurality of hidden conductors having a second orientation. Each hidden conductor includes an in-line threshold element. The three-dimensional (3D) neural network also includes synapse elements coupled between the hidden conductors and the input conductors and between the hidden conductors and the output conductor. Each synapse element includes a programmable resistive element.
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公开(公告)号:US09867734B2
公开(公告)日:2018-01-16
申请号:US14472731
申请日:2014-08-29
Applicant: Chi-Fu Chang
Inventor: Chi-Fu Chang
IPC: A61F5/56
CPC classification number: A61F5/566
Abstract: A device for reducing snoring includes a ventilation tube having an air passageway therein and a first opening and a second opening at opposite ends of the air passageway, wherein a diameter of the first end is greater than that of the second opening, and a holding member connected to the ventilation tube at an end having the first opening. Put the device of the present invention in mouth may hold a normal shape of the upper respiratory tract while the user is sleeping and ventilate the air without obstruction while the user is breathing, so the user would not snore in sleep to improve the quality of sleep.
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公开(公告)号:US20170274237A1
公开(公告)日:2017-09-28
申请号:US15460332
申请日:2017-03-16
Applicant: Chung-Fu Chang
Inventor: Chung-Fu Chang
IPC: A63B21/00 , A63B22/06 , A63B21/22 , A63B22/02 , A63B21/005 , A63B21/008
CPC classification number: A63B21/00069 , A63B21/005 , A63B21/0088 , A63B21/154 , A63B21/225 , A63B22/02 , A63B22/0605 , A63B2071/0081
Abstract: An exercise machine having a changeable damping mechanism is provided. A first transmission rope on a first shifting wheel of a first rotating shaft drives a damping device of a damping shaft to generate a relative damping action for training the leg muscular endurance of the user. Through a first changeable damping mechanism, the first transmission rope, which having stretch elasticity on the first shifting wheel is controlled to adjust the rotational speed according to the gear ratio, which may be in cooperation with a second transmission rope, which having stretch elasticity on a second shifting wheel through a second changeable damping mechanism, and is in cooperation with the damping action of a magnetic control wheel or a blower fan of the damping device to extend the range of damping control for different users to train muscular endurance.
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