公开(公告)号：US08466732B2

公开(公告)日：2013-06-18

申请号：US12900650

申请日：2010-10-08

申请人： Po-Hung Chen ,  Kuoyuan (Peter) Hsu ,  David Yen ,  Sung-Chieh Lin

发明人： Po-Hung Chen ,  Kuoyuan (Peter) Hsu ,  David Yen ,  Sung-Chieh Lin

IPC分类号： H03L5/00

CPC分类号： H03K3/356165

摘要： An input of a first inverter is configured to serve as an input node. An output of the first inverter is coupled to an input of a second inverter. An output of the second inverter is configured to serve as an output node. An input of a third inverter is coupled to an input of the first inverter. A gate of a first NMOS transistor is coupled to an output of the third inverter. A drain of the first NMOS transistor is coupled to the second inverter. A source of the first NMOS transistor is configured to serve as a level input node. When the input node is configured to receive a low logic level, the output node is configured to receive a voltage level provided by a voltage level at the level input node.

摘要翻译： 第一反相器的输入被配置为用作输入节点。 第一反相器的输出耦合到第二反相器的输入端。 第二反相器的输出被配置为用作输出节点。 第三反相器的输入耦合到第一反相器的输入端。 第一NMOS晶体管的栅极耦合到第三反相器的输出端。 第一NMOS晶体管的漏极耦合到第二反相器。 第一NMOS晶体管的源极被配置为用作电平输入节点。 当输入节点被配置为接收低逻辑电平时，输出节点被配置为接收由电平输入节点处的电压电平提供的电压电平。

公开(公告)号：US08194490B2

公开(公告)日：2012-06-05

申请号：US12877646

申请日：2010-09-08

申请人： Po-Hung Chen ,  Chin-Huang Wang ,  Yen-Chieh Huang ,  Sung-Chieh Lin ,  Kuoyuan (Peter) Hsu

发明人： Po-Hung Chen ,  Chin-Huang Wang ,  Yen-Chieh Huang ,  Sung-Chieh Lin ,  Kuoyuan (Peter) Hsu

IPC分类号： G11C17/18

CPC分类号： G11C17/165

摘要： Some embodiments regard a memory array that has a plurality of eFuse memory cells arranged in rows and columns, a plurality of bit lines, and a plurality of word lines. A column includes a bit line selector, a bit line coupled to the bit line selector, and a plurality of eFuse memory cells. An eFuse memory cell of the column includes a PMOS transistor and an eFuse. A drain of the PMOS transistor is coupled to a first end of the eFuse. A gate of the PMOS transistor is coupled to a word line. A source of the PMOS transistor is coupled to the bit line of the column.

摘要翻译： 一些实施例涉及具有以行和列，多个位线和多个字线布置的多个eFuse存储器单元的存储器阵列。 列包括位线选择器，耦合到位线选择器的位线和多个eFuse存储器单元。 该列的eFuse存储单元包括PMOS晶体管和eFuse。 PMOS晶体管的漏极耦合到eFuse的第一端。 PMOS晶体管的栅极耦合到字线。 PMOS晶体管的源极耦合到列的位线。

公开(公告)号：US08427857B2

公开(公告)日：2013-04-23

申请号：US12774851

申请日：2010-05-06

申请人： Po-Hung Chen ,  Sung-Chieh Lin ,  Kuoyuan Hsu ,  Jiann-Tseng Huang

发明人： Po-Hung Chen ,  Sung-Chieh Lin ,  Kuoyuan Hsu ,  Jiann-Tseng Huang

IPC分类号： G11C17/00

CPC分类号： G11C17/16 ,  G11C17/18

摘要： A circuit includes a fuse and a sensing and control circuit. The fuse is coupled between a MOS transistor and a current source node. The sensing and control circuit is configured to receive a programming pulse and output a modified programming signal to the gate of the MOS transistor for programming the fuse. The modified programming signal has a pulse width based on a magnitude of a current through the first fuse.

摘要翻译： 电路包括熔丝和感测和控制电路。 熔丝耦合在MOS晶体管和电流源节点之间。 感测和控制电路被配置为接收编程脉冲并将修改的编程信号输出到MOS晶体管的栅极，以编程保险丝。 改进的编程信号具有基于通过第一保险丝的电流的幅度的脉冲宽度。

公开(公告)号：US20080238439A1

公开(公告)日：2008-10-02

申请号：US11731960

申请日：2007-04-02

申请人： Sung-Chieh Lin ,  Po-Hung Chen

发明人： Sung-Chieh Lin ,  Po-Hung Chen

IPC分类号： G01R31/327

CPC分类号： G11C29/02 ,  G11C17/165 ,  G11C29/027

摘要： A method of testing a fuse element for a memory device is provided. A first test probe is electrically connected to a program terminal of the memory device. A second test probe is electrically connected to a ground terminal. The fuse element is on an electrical circuit path between the program terminal and the ground terminal. The first and second test probes are electrically connected to a testing device. A first voltage is applied with the testing device between the program terminal and the ground terminal. At least part of a first current of the first voltage flows across the fuse element. The first voltage and the at least part of the first current that flows across the fuse element is not large enough to change the conductivity state of the fuse element. The first current is measured and used to evaluated the conductive state of the fuse element.

摘要翻译： 提供一种测试用于存储器件的熔丝元件的方法。 第一测试探针电连接到存储器件的程序终端。 第二测试探针电连接到接地端子。 保险丝元件位于程序端子和接地端子之间的电路上。 第一和第二测试探针电连接到测试装置。 测试设备在程序终端和接地端子之间施加第一个电压。 第一电压的第一电流的至少一部分流过熔丝元件。 在熔断元件上流动的第一电流和第一电流的至少一部分不足以改变熔丝元件的导电状态。 测量第一电流并用于评估熔丝元件的导电状态。

公开(公告)号：US07733096B2

公开(公告)日：2010-06-08

申请号：US11731960

申请日：2007-04-02

申请人： Sung-Chieh Lin ,  Po-Hung Chen

发明人： Sung-Chieh Lin ,  Po-Hung Chen

IPC分类号： G01R31/02

CPC分类号： G11C29/02 ,  G11C17/165 ,  G11C29/027

摘要： A method of testing a fuse element for a memory device is provided. A first test probe is electrically connected to a program terminal of the memory device. A second test probe is electrically connected to a ground terminal. The fuse element is on an electrical circuit path between the program terminal and the ground terminal. The first and second test probes are electrically connected to a testing device. A first voltage is applied with the testing device between the program terminal and the ground terminal. At least part of a first current of the first voltage flows across the fuse element. The first voltage and the at least part of the first current that flows across the fuse element is not large enough to change the conductivity state of the fuse element. The first current is measured and used to evaluated the conductive state of the fuse element.

摘要翻译： 提供一种测试用于存储器件的熔丝元件的方法。 第一测试探针电连接到存储器件的程序终端。 第二测试探针电连接到接地端子。 保险丝元件位于程序端子和接地端子之间的电路上。 第一和第二测试探针电连接到测试装置。 测试设备在程序终端和接地端子之间施加第一个电压。 第一电压的第一电流的至少一部分流过熔丝元件。 在熔断元件上流动的第一电流和第一电流的至少一部分不足以改变熔丝元件的导电状态。 测量第一电流并用于评估熔丝元件的导电状态。

公开(公告)号：US20090141573A1

公开(公告)日：2009-06-04

申请号：US12124989

申请日：2008-05-21

申请人： Fu Lung Hsueh ,  Shine Chung ,  Wen-Kuan Fang ,  Po-Hung Chen

发明人： Fu Lung Hsueh ,  Shine Chung ,  Wen-Kuan Fang ,  Po-Hung Chen

IPC分类号： G11C29/00

CPC分类号： G11C29/08 ,  G11C2216/26

摘要： A system for testing logic circuits for executing writing and reading operations in a one-time programmable (OTP) memory having an array of memory cells is disclosed, the system comprising a column of testing cells having the same number of cells as that of an entire column of the array of memory cells, a row of testing cells having the same number of cells as that of an entire row of the array of memory cells, wherein both the column and row of testing cells are first written to and then read out from during a testing operation, and can never be accessed during non-testing operations of the OTP memory.

摘要翻译： 公开了一种用于测试在具有存储器单元阵列的一次可编程（OTP）存储器中执行写入和读取操作的逻辑电路的系统，该系统包括具有与整个存储器单元相同数量的单元格的测试单元列 存储单元阵列的列，一行具有与存储器单元阵列的整行相同数量的单元的测试单元，其中测试单元的列和行首先被写入然后从 在测试操作期间，并且在OTP存储器的非测试操作期间永远不能被访问。

公开(公告)号：US07405456B2

公开(公告)日：2008-07-29

申请号：US11225077

申请日：2005-09-14

申请人： Po-Hung Chen ,  Chin-Cheng Lo ,  Mao-Jung Chen

发明人： Po-Hung Chen ,  Chin-Cheng Lo ,  Mao-Jung Chen

IPC分类号： H01L29/40

CPC分类号： H01L27/14618 ,  H01L27/14625 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to an optical sensor chip package in a cavity of forming frame thereof and has a gap between protection layer and optical sensor chip. The optical sensor chip avoids accepting the pressure from protection layer that damage the reliability between pads and metallic traces when protection layer lay on the forming frame. It improves drawbacks of the glue pass trough the gap between optical sensor chip and pads into the optical sensor area of optical sensor chip. It improves the high process yield and reduces the height of optical sensor chip package to achieve lightly and thinly.

摘要翻译： 本发明涉及其形成框架的空腔中的光学传感器芯片封装，并且在保护层和光学传感器芯片之间具有间隙。 当保护层位于成型框架上时，光学传感器芯片避免接受来自保护层的压力，从而损坏焊盘和金属迹线之间的可靠性。 它改善了光学传感器芯片和焊盘之间的间隙的胶合通过光学传感器芯片的光学传感器区域的缺点。 它提高了高工艺成品率，降低了光学传感器芯片封装的高度，实现轻薄。

公开(公告)号：US20070090478A1

公开(公告)日：2007-04-26

申请号：US11251777

申请日：2005-10-18

申请人： Po-Hung Chen ,  Mao-Jung Chen

发明人： Po-Hung Chen ,  Mao-Jung Chen

IPC分类号： H01L31/0203

CPC分类号： H01L27/14618 ,  H01L27/14683 ,  H01L31/0203 ,  H01L2924/0002 ,  H01L2924/00

摘要： An image sensor package structure is proposed, in which an image sensor is fixed on a substrate having metallization traces and an adhesion layer. Electric paths of the package structure are changed from the COG (chip on glass) process to the CIS (CMOS image sensor) process to improve electric characteristics. Moreover, spacers are formed at appropriate positions to prevent glue overflow from contaminating the sensing regions and solder balls. The proposed package structure can also shrink the package area to greatly enhance the yield and quality.

摘要翻译： 提出了一种图像传感器封装结构，其中图像传感器固定在具有金属化迹线和粘合层的基板上。 封装结构的电气路径从COG（玻璃上芯片）工艺转变为CIS（CMOS图像传感器）工艺，以改善电气特性。 而且，在适当的位置形成间隔物，以防止胶水溢出污染感测区域和焊球。 提出的包装结构也可以缩小包装面积，大大提高产量和质量。

公开(公告)号：US20190123476A1

公开(公告)日：2019-04-25

申请号：US16124200

申请日：2018-09-07

申请人： Po-Hung Chen

发明人： Po-Hung Chen

IPC分类号： H01R13/506 ,  H01R12/71 ,  H01R13/405 ,  H01R13/6585

CPC分类号： H01R13/506 ,  H01R12/716 ,  H01R13/405 ,  H01R13/6275 ,  H01R13/6583 ,  H01R13/6585 ,  H01R24/60 ,  H01R2107/00

摘要： A connector with latch protection includes a metal casing, an insulating body, plural metal terminals and a partition. The insulating body covers the interior of the metal casing and has a tab extended forwardly from the front of the insulating body and disposed apart on the top and bottom of the tab respectively, and both sides of the tab corresponding to a connecting plug form an inwardly concave portion, and both sides of the partition have a protection plate corresponding to each inwardly concave portion and the front of the tab and bent and extended forwardly. When the partition is embedded into the insulating body by a molding method, a portion of the two metal protection plates exposed from the tab forms a pair of latch grooves for latching the connecting plug to effectively improve the durability and life and lower the manufacturing cost of the connector significantly.

公开(公告)号：US09000751B2

公开(公告)日：2015-04-07

申请号：US13396235

申请日：2012-02-14

申请人： Po-Hung Chen ,  Makoto Takamiya ,  Takayasu Sakurai

发明人： Po-Hung Chen ,  Makoto Takamiya ,  Takayasu Sakurai

IPC分类号： G01R1/30 ,  G01R19/165 ,  G01F3/20

CPC分类号： G01R19/16519 ,  G01F3/20

摘要： In a voltage detecting circuit, a transistor is configured as a P-type MOSFET, and includes a source connected with an input terminal, a gate connected with a ground voltage terminal and a drain connected with an output terminal. A transistor is configured as a P-type MOSFET, and includes a gate and a source connected with the output terminal and a drain connected with the ground terminal. Gate width and gate length of the transistor and gate width and gate length of the transistor are adjusted so that source-drain current flowing between the source and the drain of the transistor becomes equal to source-drain current flowing between the source and the drain of the transistor when the voltage applied to the input terminal is set to be preset trigger voltage. This configuration accomplishes detecting that the input voltage exceeds the trigger voltage with simple configuration.

摘要翻译： 在电压检测电路中，晶体管被配置为P型MOSFET，并且包括与输入端连接的源极，与接地电压端子连接的栅极和与输出端子连接的漏极。 晶体管被配置为P型MOSFET，并且包括与输出端连接的栅极和源极以及与接地端子连接的漏极。 调节晶体管的栅极宽度和栅极长度，并调整晶体管的栅极宽度和栅极长度，使得在晶体管的源极和漏极之间流动的源极 - 漏极电流变得等于在源极和漏极之间流动的源极 - 漏极电流 当施加到输入端子的电压被设置为预置触发电压时，晶体管。 该配置通过简单的配置实现了输入电压超过触发电压的检测。