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    Voltage detecting circuit
    1.
    发明授权
    Voltage detecting circuit 有权
    电压检测电路

    公开(公告)号：US09000751B2

    公开(公告)日：2015-04-07

    申请号：US13396235

    申请日：2012-02-14

    申请人： Po-Hung Chen ,  Makoto Takamiya ,  Takayasu Sakurai

    发明人： Po-Hung Chen ,  Makoto Takamiya ,  Takayasu Sakurai

    IPC分类号： G01R1/30 ,  G01R19/165 ,  G01F3/20

    CPC分类号： G01R19/16519 ,  G01F3/20

    摘要： In a voltage detecting circuit, a transistor is configured as a P-type MOSFET, and includes a source connected with an input terminal, a gate connected with a ground voltage terminal and a drain connected with an output terminal. A transistor is configured as a P-type MOSFET, and includes a gate and a source connected with the output terminal and a drain connected with the ground terminal. Gate width and gate length of the transistor and gate width and gate length of the transistor are adjusted so that source-drain current flowing between the source and the drain of the transistor becomes equal to source-drain current flowing between the source and the drain of the transistor when the voltage applied to the input terminal is set to be preset trigger voltage. This configuration accomplishes detecting that the input voltage exceeds the trigger voltage with simple configuration.

    摘要翻译： 在电压检测电路中，晶体管被配置为P型MOSFET，并且包括与输入端连接的源极，与接地电压端子连接的栅极和与输出端子连接的漏极。 晶体管被配置为P型MOSFET，并且包括与输出端连接的栅极和源极以及与接地端子连接的漏极。 调节晶体管的栅极宽度和栅极长度，并调整晶体管的栅极宽度和栅极长度，使得在晶体管的源极和漏极之间流动的源极 - 漏极电流变得等于在源极和漏极之间流动的源极 - 漏极电流 当施加到输入端子的电压被设置为预置触发电压时，晶体管。 该配置通过简单的配置实现了输入电压超过触发电压的检测。

    INTEGRATED CIRCUIT DEVICE
    2.
    发明申请
    INTEGRATED CIRCUIT DEVICE 有权
    集成电路设备

    公开(公告)号：US20140104952A1

    公开(公告)日：2014-04-17

    申请号：US14118464

    申请日：2012-05-11

    申请人： Ken Takeuchi ,  Teruyoshi Hatanaka ,  Koichi Ishida ,  Tadashi Yasufuku ,  Makoto Takamiya ,  Takayasu Sakurai

    发明人： Ken Takeuchi ,  Teruyoshi Hatanaka ,  Koichi Ishida ,  Tadashi Yasufuku ,  Makoto Takamiya ,  Takayasu Sakurai

    IPC分类号： H02M3/155 ,  G11C16/30

    CPC分类号： H02M3/155 ,  G11C16/06 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3418 ,  H02M3/158 ,  H02M2001/007

    摘要： A booster circuit is configured, such that: in response to a reading request for reading data from a flash memory, when a voltage of an output terminal detected by a voltage detection circuit is not higher than a voltage, an oscillator outputs a control clock signal of predetermined on time and off time to a transistor of a boost converter to perform switching control of the transistor; and when the voltage detection circuit detects that the voltage of the output terminal reaches a voltage, an oscillator outputs a control clock signal of an on time and an off time input from a selection circuit to a transistor of a boost converter to perform switching control of the transistor.

    摘要翻译： 升压电路被配置为：响应于从闪速存储器读取数据的读取请求，当由电压检测电路检测到的输出端子的电压不高于电压时，振荡器输出控制时钟信号 对升压转换器的晶体管进行预定的时间和关断时间，以执行晶体管的切换控制; 并且当电压检测电路检测到输出端子的电压达到电压时，振荡器输出从选择电路输入到升压转换器的晶体管的接通时间和截止时间的控制时钟信号，以执行切换控制 晶体管。

    Integrated circuit device having a plurality of integrated circuit chips and an interposer
    3.
    发明授权
    Integrated circuit device having a plurality of integrated circuit chips and an interposer 有权
    具有多个集成电路芯片和插入器的集成电路装置

    公开(公告)号：US08514013B2

    公开(公告)日：2013-08-20

    申请号：US13093343

    申请日：2011-04-25

    申请人： Ken Takeuchi ,  Teruyoshi Hatanaka ,  Koichi Ishida ,  Tadashi Yasufuku ,  Makoto Takamiya ,  Takayasu Sakurai

    发明人： Ken Takeuchi ,  Teruyoshi Hatanaka ,  Koichi Ishida ,  Tadashi Yasufuku ,  Makoto Takamiya ,  Takayasu Sakurai

    IPC分类号： H01L25/00

    CPC分类号： H01L25/0657 ,  H01L25/18 ,  H01L2225/06565 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The channel number detecting circuit detects the operation channel number based on the output terminal voltage after falling down when the output terminal voltage falls down during the voltage boosting control, and the switching control circuit generates the control clock signal having the on-time and the off-time adjusted based on the operation channel number and performs the voltage boosting control using generating control clock signal. The voltage boosting control is properly performed based on the operation channel number when the operation channel number increase during performing the voltage boosting control. Thus boosting the power supply voltage up to a second voltage is accomplished.

    摘要翻译： 通道号检测电路在升压控制期间当输出端子电压下降时，基于输出端子电压在下降之后检测操作通道数，并且开关控制电路产生具有导通时间和关断的控制时钟信号 根据操作通道号进行时间调整，并使用产生控制时钟信号进行升压控制。 当在执行升压控制期间操作通道号增加时，基于操作通道号适当地执行升压控制。 从而实现将电源电压提高到第二电压。

    Voltage characteristic regulating method of latch circuit, voltage characteristic regulating method of semiconductor device, and voltage characteristic regulator of latch circuit
    7.
    发明授权
    Voltage characteristic regulating method of latch circuit, voltage characteristic regulating method of semiconductor device, and voltage characteristic regulator of latch circuit 失效
    锁存电路的电压特性调节方法，半导体器件的电压特性调节方法和锁存电路的电压特性调节器

    公开(公告)号：US08618870B2

    公开(公告)日：2013-12-31

    申请号：US13377009

    申请日：2010-06-11

    申请人： Toshiro Hiramoto ,  Takayasu Sakurai ,  Makoto Suzuki

    发明人： Toshiro Hiramoto ,  Takayasu Sakurai ,  Makoto Suzuki

    IPC分类号： G05F1/10

    CPC分类号： G11C11/413

    摘要： The voltage Vdd is set to be lower than in the normal operation (step S100), then voltage is applied to each of the power-supply voltage applied node Vdd, the ground voltage applied node Vss, the semiconductor substrate and the well so that relative high voltage between the gate of turn-on transistor and the semiconductor substrate or the gate of turn-on transistor and well (steps S110 and S120). This process accomplishes rising of the threshold voltage of the transistor that is turned on, the reduction of the variation in the threshold voltage between a plurality of the transistors of the memory cell including latch circuit, and the improvement of the voltage characteristic of the memory cell.

    摘要翻译： 电压Vdd被设定为低于正常工作（步骤S100），然后对电源电压施加节点Vdd，接地电压施加节点Vss，半导体衬底和阱施加电压，使得相对 导通晶体管的栅极与半导体衬底或导通晶体管的栅极之间的高电压（步骤S110和S120）。 该处理完成导通的晶体管的阈值电压的上升，包括锁存电路的存储单元的多个晶体管之间的阈值电压的变化的减小以及存储单元的电压特性的改善 。

    Self-aligned row-by-row dynamic VDD SRAM
    8.
    发明申请
    Self-aligned row-by-row dynamic VDD SRAM 失效
    自对准逐行动态VDD SRAM

    公开(公告)号：US20060039182A1

    公开(公告)日：2006-02-23

    申请号：US11205466

    申请日：2005-08-16

    申请人： Takayasu Sakurai ,  Hiroshi Kawaguchi ,  Robert Fayez

    发明人： Takayasu Sakurai ,  Hiroshi Kawaguchi ,  Robert Fayez

    IPC分类号： G11C11/00

    CPC分类号： G11C11/413

    摘要： A memory cell array includes a plurality of memory cells arranged in a matrix form. A word line and a power supply line respectively are connected in common to the plurality of memory cells arranged in each row. A power supply line/word line control circuit is connected to each word line and each power supply line. In accessing the plurality of memory cells row by row, the control circuit raises the voltage of the power supply line and, after the voltage of the power supply line reaches the high voltage at all the positions, starts activation of the word line. On the other hand, in turning from the access state to the non-access state, the control circuit deactivates the word line and, after the voltage of the word line changes to the ground voltage at all the positions, changes the voltage of the power supply line to the low voltage.

    摘要翻译： 存储单元阵列包括以矩阵形式布置的多个存储单元。 字线和电源线分别连接到布置在每一行中的多个存储单元。 电源线/字线控制电路连接到每个字线和每个电源线。 在逐行访问多个存储单元时，控制电路提高电源线的电压，并且在所有位置的电源线的电压达到高电压之后，开始字线的激活。 另一方面，在从访问状态转到非访问状态时，控制电路使字线停止，并且在字线的电压在所有位置变化为接地电压之后，改变电源的电压 供电线路为低电压。

    ECL output buffer with a MOS transistor used for tristate enable
    9.
    发明授权
    ECL output buffer with a MOS transistor used for tristate enable 失效
    具有用于三态使能的MOS晶体管的ECL输出缓冲器

    公开(公告)号：US5434517A

    公开(公告)日：1995-07-18

    申请号：US215174

    申请日：1994-03-21

    申请人： Hiroyuki Hara ,  Takayasu Sakurai

    发明人： Hiroyuki Hara ,  Takayasu Sakurai

    IPC分类号： H03K19/08 ,  H03K19/018 ,  H03K19/082 ,  H03K19/086

    CPC分类号： H03K19/01812 ,  H03K19/0826

    摘要： An ECL output buffer circuit is constituted by an output buffer circuit main portion and its control circuit. In the output buffer circuit main portion, an output from a differential switch is input to the base of a bipolar transistor (emitter follower). The emitter of the bipolar transistor is connected to an output terminal. A ground potential is applied to the collector of the bipolar transistor. One end of the channel conductive path of a MOS transistor is connected to the base of the bipolar transistor. The other end of the channel conductive path is connected to a power-supply terminal via a constant-current source. The control circuit controls the ON/OFF operation of the MOS transistor and the output level of the bipolar transistor. When the output buffer circuit main portion is to be set in a standby state, the control circuit performs control to set the MOS transistor in an ON state and set the output of the bipolar transistor at low level.

    摘要翻译： ECL输出缓冲电路由输出缓冲电路主要部分及其控制电路构成。 在输出缓冲电路主要部分中，差分开关的输出被输入到双极晶体管（射极跟随器）的基极。 双极晶体管的发射极连接到输出端子。 接地电位施加到双极晶体管的集电极。 MOS晶体管的沟道导电路径的一端连接到双极晶体管的基极。 通道导电路径的另一端经由恒流源与电源端子连接。 控制电路控制MOS晶体管的ON / OFF操作和双极晶体管的输出电平。 当输出缓冲器电路主要部分被设置在待机状态时，控制电路进行控制以将MOS晶体管设置在导通状态，并将双极晶体管的输出设置为低电平。

    Semiconductor memory device having a function of simultaneously clearing part of memory data
    10.
    发明授权
    Semiconductor memory device having a function of simultaneously clearing part of memory data 失效
    具有同时清除部分存储器数据的功能的半导体存储器件

    公开(公告)号：US4958326A

    公开(公告)日：1990-09-18

    申请号：US274555

    申请日：1988-11-22

    申请人： Takayasu Sakurai

    发明人： Takayasu Sakurai

    IPC分类号： G11C11/401 ,  G11C7/20 ,  G11C8/12

    CPC分类号： G11C7/20 ,  G11C8/12

    摘要： A semiconductor memory device includes a first memory cell array and a second memory cell array section into which the same data can be simultaneously written. Logic gates are provided between the word lines of the first memory cell array section and the respective word lines of the second memory cell array section. In the normal operation mode, the logic gates connect each of the rows of memory cells in the first memory cell array section to a corresponding one of the rows of memory cells in the second memory cell array section, and set each of the rows of memory cells in the second memory cell array section to a selected level when the same data is simultaneously written into the memory cells of the second memory cell array section. When each of the rows of memory cells in the second memory cell array section is set to the selected level, all the columns of the memory cells in the second memory cell array section are simultaneously selected and the same data is simultaneously written into the second memory cell array section.