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公开(公告)号：US08466732B2
公开(公告)日：2013-06-18
申请号：US12900650
申请日：2010-10-08
申请人： Po-Hung Chen , Kuoyuan (Peter) Hsu , David Yen , Sung-Chieh Lin
发明人： Po-Hung Chen , Kuoyuan (Peter) Hsu , David Yen , Sung-Chieh Lin
IPC分类号： H03L5/00
CPC分类号： H03K3/356165
摘要： An input of a first inverter is configured to serve as an input node. An output of the first inverter is coupled to an input of a second inverter. An output of the second inverter is configured to serve as an output node. An input of a third inverter is coupled to an input of the first inverter. A gate of a first NMOS transistor is coupled to an output of the third inverter. A drain of the first NMOS transistor is coupled to the second inverter. A source of the first NMOS transistor is configured to serve as a level input node. When the input node is configured to receive a low logic level, the output node is configured to receive a voltage level provided by a voltage level at the level input node.
摘要翻译： 第一反相器的输入被配置为用作输入节点。 第一反相器的输出耦合到第二反相器的输入端。 第二反相器的输出被配置为用作输出节点。 第三反相器的输入耦合到第一反相器的输入端。 第一NMOS晶体管的栅极耦合到第三反相器的输出端。 第一NMOS晶体管的漏极耦合到第二反相器。 第一NMOS晶体管的源极被配置为用作电平输入节点。 当输入节点被配置为接收低逻辑电平时，输出节点被配置为接收由电平输入节点处的电压电平提供的电压电平。
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公开(公告)号：US08194490B2
公开(公告)日：2012-06-05
申请号：US12877646
申请日：2010-09-08
IPC分类号： G11C17/18
CPC分类号： G11C17/165
摘要： Some embodiments regard a memory array that has a plurality of eFuse memory cells arranged in rows and columns, a plurality of bit lines, and a plurality of word lines. A column includes a bit line selector, a bit line coupled to the bit line selector, and a plurality of eFuse memory cells. An eFuse memory cell of the column includes a PMOS transistor and an eFuse. A drain of the PMOS transistor is coupled to a first end of the eFuse. A gate of the PMOS transistor is coupled to a word line. A source of the PMOS transistor is coupled to the bit line of the column.
摘要翻译： 一些实施例涉及具有以行和列，多个位线和多个字线布置的多个eFuse存储器单元的存储器阵列。 列包括位线选择器，耦合到位线选择器的位线和多个eFuse存储器单元。 该列的eFuse存储单元包括PMOS晶体管和eFuse。 PMOS晶体管的漏极耦合到eFuse的第一端。 PMOS晶体管的栅极耦合到字线。 PMOS晶体管的源极耦合到列的位线。
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公开(公告)号：US08400860B2
公开(公告)日：2013-03-19
申请号：US12839542
申请日：2010-07-20
IPC分类号： G11C17/16
CPC分类号： G11C17/16
摘要： Some embodiments regard a memory array that has a plurality of rows and columns. A column includes a program control device, a plurality of eFuse memory cells in the column, a sense amplifier, and a bit line coupling the program control device, the plurality of memory cells in the column, and the sense amplifier. A row includes a plurality of eFuse memory cells in the row, a word line coupling the plurality of eFuse memory cells in the row, and a footer configured as a current path for the plurality of eFuse memory cells in the row.
摘要翻译： 一些实施例涉及具有多个行和列的存储器阵列。 列包括程序控制装置，列中的多个eFuse存储器单元，读出放大器和耦合程序控制装置，列中的多个存储单元和读出放大器的位线。 行包括行中的多个eFuse存储器单元，耦合行中的多个eFuse存储器单元的字线和被配置为行中的多个eFuse存储器单元的当前路径的页脚。
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4.发明授权Integrated circuit structure to resolve deep-well plasma charging problem and method of forming the same 有权集成电路结构解决深井等离子体充电问题及其形成方法公开(公告)号：US08946825B2
公开(公告)日：2015-02-03
申请号：US13433194
申请日：2012-03-28
申请人： David Yen , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
发明人： David Yen , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
IPC分类号： H01L23/62
CPC分类号： H01L27/0928 , H01L21/263 , H01L21/823871 , H01L21/823878 , H01L21/823892 , H01L27/0629 , H01L29/6609
摘要： During various processing operations, ions from process plasma may be transfer to a deep n-well (DNW) formed under devices structures. A reverse-biased diode may be connected to the signal line to protect a gate dielectric formed outside the DNW and is connected to the drain of the transistor formed inside the DNW.
摘要翻译： 在各种处理操作期间，来自工艺等离子体的离子可以转移到在器件结构下形成的深n阱（DNW）。 反向偏置二极管可以连接到信号线以保护形成在DNW外部的栅极电介质，并且连接到形成在DNW内部的晶体管的漏极。
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公开(公告)号：US08824234B2
公开(公告)日：2014-09-02
申请号：US13771674
申请日：2013-02-20
IPC分类号： G11C17/16
CPC分类号： G11C17/16
摘要： A method of reading an eFuse in a column of eFuse memory cells includes electrically disconnecting a first end of the eFuse from a first electrical path. A second electrical path between a second end of the eFuse and a node is activated to bypass a third electrical path, where the third electrical path includes a diode device between the second end of the eFuse and the node. A footer coupled with the node is turned on.
摘要翻译： 读取eFuse存储单元列中的eFuse的方法包括将eFuse的第一端与第一电路断开。 eFuse的第二端和节点之间的第二电路被激活以绕过第三电路，其中第三电路包括在eFuse的第二端和节点之间的二极管器件。 与节点耦合的页脚被打开。
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公开(公告)号：US08625324B2
公开(公告)日：2014-01-07
申请号：US13107441
申请日：2011-05-13
申请人： Sung-Chieh Lin , David Yen , Chi-Hsu Chiu , Kuoyuan (Peter) Hsu
发明人： Sung-Chieh Lin , David Yen , Chi-Hsu Chiu , Kuoyuan (Peter) Hsu
CPC分类号： H01L23/5256 , G11C17/10 , G11C17/16 , H01L2924/0002 , H01L2924/00
摘要： The embodiments of methods and structures disclosed herein provide mechanisms of forming and programming a non-salicided polysilicon fuse. The non-salicided polysilicon fuse and a programming transistor form a one-time programmable (OTP) memory cell, which can be programmed with a low programming voltage.
摘要翻译： 本文公开的方法和结构的实施例提供了形成和编程非水化多晶硅熔丝的机制。 非水银多晶硅熔丝和编程晶体管形成一个可编程的编程电压低的一次可编程（OTP）存储单元。
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公开(公告)号：US09135099B2
公开(公告)日：2015-09-15
申请号：US13434588
申请日：2012-03-29
CPC分类号： G06F11/073 , G06F11/0793 , G06F11/1008 , H03M13/19 , H03M13/6561
摘要： A method includes, by a first circuit, converting a plurality of bits in a first format to a second format. The plurality of bits in the second format is used, by a second circuit, to program a plurality of memory cells corresponding to the plurality of bits. The first format is a parallel format. The second format is a serial format. The first circuit and the second circuit are electrically coupled together in a chip. In some embodiments, the plurality of bits includes address information, cell data information, and program information of a memory cell that has an error. In some embodiments, the plurality of bits includes word data information of a word and error code and correction information corresponding to the word data information of the word.
摘要翻译： 一种方法包括通过第一电路将第一格式的多个比特转换成第二格式。 通过第二电路使用第二格式的多个比特来对与多个比特相对应的多个存储单元进行编程。 第一种格式是并行格式。 第二种格式是串行格式。 第一电路和第二电路在芯片中电耦合在一起。 在一些实施例中，多个位包括地址信息，单元数据信息和具有错误的存储器单元的程序信息。 在一些实施例中，多个比特包括单词的字数据信息和与单词的单词数据信息对应的错误代码和校正信息。
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公开(公告)号：US08760955B2
公开(公告)日：2014-06-24
申请号：US13278686
申请日：2011-10-21
申请人： Wei-Li Liao , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
发明人： Wei-Li Liao , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
IPC分类号： G11C17/16
摘要： A mechanism of reconfiguring an eFuse memory array to have two or more neighboring eFuse bit cells placed side by and side and sharing a program bit line. By allowing two or more neighboring eFuse bit cells to share a program bit line, the length of the program bit line is shortened, which results in lower resistivity of the program bit line. The width of the program bit line may also be increased to further reduce the resistivity of program bit line. Program bit lines with low resistance and high current are needed for advanced eFuse memory arrays using low-resistivity eFuses.
摘要翻译： 重新配置eFuse存储器阵列以使两个或更多个相邻的eFuse位单元被放置在旁边并共享一个程序位线的机制。 通过允许两个或多个相邻的eFuse位单元共享程序位线，程序位线的长度被缩短，这导致程序位线的电阻较低。 也可以增加编程位线的宽度，以进一步降低程序位线的电阻率。 使用低电阻率eFuse的高级eFuse存储器阵列需要具有低电阻和高电流的程序位线。
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公开(公告)号：US08614927B2
公开(公告)日：2013-12-24
申请号：US13595551
申请日：2012-08-27
IPC分类号： G11C7/00
摘要： This description relates to a circuit including a bit line. The circuit further includes at least one memory bank. The at least one memory bank includes at least one memory cell, a first device configured to provide a current path between the bit line and the at least one memory cell when the at least one memory cell is activated, and a second device configured to reduce current leakage between the bit line and the at least one memory cell when the at least one memory cell is deactivated. The circuit further includes a tracking device configured to receive a mirror current substantially equal to a current along the current path, the tracking device configured to have a resistance substantially equal to a cumulative resistance of all memory cells of the at least one memory cell.
摘要翻译： 本说明书涉及包括位线的电路。 电路还包括至少一个存储体。 所述至少一个存储体包括至少一个存储单元，配置为当所述至少一个存储单元被激活时在所述位线和所述至少一个存储器单元之间提供电流路径的第一设备，以及被配置为减少 当所述至少一个存储器单元被停用时，所述位线与所述至少一个存储器单元之间的电流泄漏。 电路还包括跟踪装置，其被配置为接收基本上等于沿着电流路径的电流的反射镜电流，跟踪装置被配置为具有基本上等于至少一个存储器单元的所有存储器单元的累积电阻的电阻。
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公开(公告)号：US20130221995A1
公开(公告)日：2013-08-29
申请号：US13407548
申请日：2012-02-28
CPC分类号： G01R27/08 , G11C7/062 , G11C17/18 , G11C2207/063 , H03F3/45179 , H03F2200/555 , H03F2203/45394 , H03F2203/45674
摘要： An amplifying circuit comprises a bias circuit, a reference circuit, a first circuit, and an amplifying sub-circuit. The bias circuit is configured to provide a bias current. The reference circuit is configured to provide a first differential input based on a reference resistive device and a reference current derived from the bias current. The first circuit is configured to provide a second differential input based on a first current and a first resistance. The amplifying sub-circuit is configured to receive the first differential input and the second differential input and to generate a sense amplifying output indicative of a resistance relationship between the first resistance and a resistance of the reference resistive device.
摘要翻译： 放大电路包括偏置电路，参考电路，第一电路和放大子电路。 偏置电路被配置为提供偏置电流。 参考电路被配置为提供基于参考电阻器件的第一差分输入和从偏置电流导出的参考电流。 第一电路被配置为基于第一电流和第一电阻提供第二差分输入。 放大子电路被配置为接收第一差分输入和第二差分输入，并且产生指示第一电阻和参考电阻器件的电阻之间的电阻关系的读出放大输出。
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