公开(公告)号：US20220109444A1

公开(公告)日：2022-04-07

申请号：US17175570

申请日：2021-02-12

申请人： POSTECH Research and Business Development Foundation

发明人： Seokhyeong KANG ,  Sunghye PARK ,  SungYun LEE ,  Sunmean KIM

IPC分类号： H03K19/00 ,  H01L51/05 ,  G06F30/327 ,  G06F30/337

摘要： A static ternary gate is disclosed. The static ternary gate includes a drain-ground path configured to output a drain voltage through a first transistor when a first pull-up circuit is turned on, and output a ground voltage through a second transistor when a first pull-down circuit is turned on, a half-drain path configured to output a half-drain voltage through the first transistor and the second transistor when both a second pull-up circuit and a second pull-down circuit are turned on. The first transistor is configured to connect a node between the first pull-up circuit and the second pull-down circuit to an output terminal, and the second transistor is configured to connect a node between the second pull-up circuit and the first pull-down circuit to the output terminal.

公开(公告)号：US20220352893A1

公开(公告)日：2022-11-03

申请号：US17489624

申请日：2021-09-29

申请人： POSTECH Research and Business Development Foundation

发明人： Seokhyeong KANG ,  Sunmean KIM ,  SungYun LEE ,  Sunghye PARK

IPC分类号： H03K19/0944 ,  H03K19/20

摘要： A circuit includes a plurality of first counting gates, a first ternary half adder (THA) and a second THA that are connected to the plurality of first counting gates, a third THA configured to receive a sum output signal of the first THA and a sum output signal of the second THA, a first ternary sum gate configured to receive a carry output signal of the first THA and a carry output signal of the second THA, and a second ternary sum gate configured to receive a carry output signal of the third THA and an output signal of the first ternary sum gate, wherein the third THA and the second ternary sum gate may be configured to output voltage signals corresponding to a number of drain voltages among input signals applied to the plurality of first counting gates.

公开(公告)号：US20220350568A1

公开(公告)日：2022-11-03

申请号：US17489629

申请日：2021-09-29

申请人： Postech Research and Business Development Foundation

发明人： Seokhyeong KANG ,  Sunmean KIM ,  Sunghye PARK ,  SungYun LEE

IPC分类号： G06F7/502 ,  H03K19/173

摘要： A circuit includes a first full adder, a second full adder, a first half adder, a third full adder configured to receive a sum output signal of the first full adder, a sum output signal of the second full adder, and a sum output signal of the first half adder, a fourth full adder configured to receive a carry output signal of the first full adder, a carry output signal of the second full adder, and a carry output signal of the first half adder, a second half adder configured to receive a carry output signal of the third full adder and a sum output signal of the fourth full adder, and a third half adder configured to receive a carry output signal of the second half adder and a carry output signal of the fourth full adder.