公开(公告)号：US20170024570A1

公开(公告)日：2017-01-26

申请号：US14974960

申请日：2015-12-18

申请人： Pradeep M. Pappachan ,  Reshma Lal ,  Bin Xing ,  Siddhartha Chhabra ,  Vincent R. Scarlata ,  Steven B. McGowan

发明人： Pradeep M. Pappachan ,  Reshma Lal ,  Bin Xing ,  Siddhartha Chhabra ,  Vincent R. Scarlata ,  Steven B. McGowan

IPC分类号： G06F21/60 ,  G06F13/28

CPC分类号： G06F21/602 ,  G06F13/28 ,  G06F21/57

摘要： Technologies for trusted I/O attestation and verification include a computing device with a cryptographic engine and one or more I/O controllers. The computing device collects hardware attestation information associated with statically attached hardware I/O components that are associated with a trusted I/O usage protected by the cryptographic engine. The computing device verifies the hardware attestation information and securely enumerates one or more dynamically attached hardware components in response to verification. The computing device collects software attestation information for trusted software components loaded during secure enumeration. The computing device verifies the software attestation information. The computing device may collect firmware attestation information for firmware loaded in the I/O controllers and verify the firmware attestation information. The computing device may collect application attestation information for a trusted application that uses the trusted I/O usage and verify the application attestation information. Other embodiments are described and claimed.

摘要翻译： 用于可信I / O认证和验证的技术包括具有加密引擎和一个或多个I / O控制器的计算设备。 计算设备收集与由加密引擎保护的受信任的I / O使用相关联的静态附接的硬件I / O组件相关联的硬件认证信息。 计算设备验证硬件认证信息并且响应于验证安全地枚举一个或多个动态附加的硬件组件。 计算设备收集在安全枚举期间加载的可信软件组件的软件认证信息。 计算设备验证软件认证信息。 计算设备可以收集加载在I / O控制器中的固件的固件证明信息，并验证固件证明信息。 计算设备可以收集使用可信I / O使用的可信应用的应用认证信息，并验证应用认证信息。 描述和要求保护其他实施例。

公开(公告)号：US20170024584A1

公开(公告)日：2017-01-26

申请号：US14979002

申请日：2015-12-22

申请人： Siddhartha Chhabra ,  Gideon Gerzon ,  Reshma Lal ,  Bin Xing ,  Pradeep M. Pappachan ,  Steven B. McGowan

发明人： Siddhartha Chhabra ,  Gideon Gerzon ,  Reshma Lal ,  Bin Xing ,  Pradeep M. Pappachan ,  Steven B. McGowan

IPC分类号： G06F21/72 ,  H04L9/32 ,  H04L9/08

CPC分类号： G06F21/72 ,  G06F21/57 ,  H04L9/0822 ,  H04L9/0861 ,  H04L9/3242

摘要： Technologies for secure programming of a cryptographic engine include a computing device with a cryptographic engine and one or more I/O controllers. The computing device establishes, an invoking secure enclave using secure enclave support of a processor. The invoking enclave configures channel programming information, including a channel key, and invokes a processor instruction with the channel programming information as a parameter. The processor generates wrapped programming information including an encrypted channel key and a message authentication code. The encrypted channel key is protected with a key known only to the processor. The invoking enclave provides the wrapped programming information to untrusted software, which invokes a processor instruction with the wrapped programming information as a parameter. The processor unwraps and verifies the wrapped programming information and then programs the cryptographic engine. The processor generates an authenticated response that may be verified by the invoking enclave. Other embodiments are described and claimed.

摘要翻译： 用于加密引擎的安全编程的技术包括具有密码引擎和一个或多个I / O控制器的计算设备。 计算设备使用处理器的安全飞地支持来建立调用安全飞地。 调用飞地配置信道编程信息，包括信道密钥，并且以通道编程信息为参数来调用处理器指令。 处理器产生包括加密的信道密钥和消息认证码的包装节目信息。 加密的通道密钥由仅对处理器已知的密钥进行保护。 调用的包层将包装的编程信息提供给不受信任的软件，该软件以包装的编程信息作为参数调用处理器指令。 处理器解封装并验证封装的编程信息，然后对加密引擎进行编程。 处理器生成可以通过调用飞地验证的认证响应。 描述和要求保护其他实施例。

公开(公告)号：US20170024568A1

公开(公告)日：2017-01-26

申请号：US14974874

申请日：2015-12-18

申请人： Pradeep M. Pappachan ,  Reshma Lal ,  Bin Xing ,  Steven B. McGowan ,  Siddhartha Chhabra ,  Reouven Elbaz

发明人： Pradeep M. Pappachan ,  Reshma Lal ,  Bin Xing ,  Steven B. McGowan ,  Siddhartha Chhabra ,  Reouven Elbaz

IPC分类号： G06F21/60 ,  G06F13/28 ,  G06F17/30

CPC分类号： G06F21/602 ,  G06F13/28 ,  G06F17/30371 ,  G06F21/606 ,  G06F21/64 ,  G06F2221/031

摘要： Technologies for authenticity assurance for I/O data include a computing device with a cryptographic engine and one or more I/O controllers. A metadata producer of the computing device performs an authenticated encryption operation on I/O data to generate encrypted I/O data and an authentication tag. The metadata producer stores the encrypted I/O data in a DMA buffer and the authentication tag in an authentication tag queue. A metadata consumer decrypts the encrypted I/O data from the DMA buffer and determines whether the encrypted I/0 data is authentic using the authentication tag from the authentication tag queue. For input, the metadata producer may be embodied as the cryptographic engine and the metadata consumer may be embodied as a trusted software component. For output, the metadata producer may be embodied as the trusted software component and the metadata consumer may be embodied as the cryptographic engine. Other embodiments are described and claimed.

摘要翻译： 用于I / O数据的真实性保证的技术包括具有加密引擎和一个或多个I / O控制器的计算设备。 计算设备的元数据生成器对I / O数据执行认证加密操作以产生加密的I / O数据和认证标签。 元数据生成器将加密的I / O数据存储在DMA缓冲器中，认证标签存储在认证标签队列中。 元数据消费者从DMA缓冲器解密加密的I / O数据，并使用来自认证标签队列的认证标签来确定加密的I / O数据是否是真实的。 对于输入，元数据生成器可以体现为加密引擎，并且元数据消费者可以被实现为可信软件组件。 对于输出，元数据生成器可以被实现为可信软件组件，并且元数据消费者可以被体现为密码引擎。 描述和要求保护其他实施例。

公开(公告)号：US20170026181A1

公开(公告)日：2017-01-26

申请号：US14974948

申请日：2015-12-18

申请人： Siddhartha Chhabra ,  Reshma Lal ,  Ravi L. Sahita ,  Reouven Elbaz ,  Bin Xing

发明人： Siddhartha Chhabra ,  Reshma Lal ,  Ravi L. Sahita ,  Reouven Elbaz ,  Bin Xing

IPC分类号： H04L9/32 ,  G06F9/455 ,  G06F21/53 ,  G06F13/28

CPC分类号： H04L9/3234 ,  G06F9/45558 ,  G06F13/28 ,  G06F21/53 ,  G06F2009/45579 ,  G06F2009/45587 ,  G06F2221/2149 ,  H04L2209/127 ,  H04L2209/26

摘要： Technologies for secure programming of a cryptographic engine include a computing device with a cryptographic engine and one or more I/O controllers. The computing device establishes one or more trusted execution environments (TEEs). A TEE generates a request to program the cryptographic engine with respect to a DMA channel. The computing device may verify a signed manifest that indicates the TEEs permitted to program DMA channels and, if verified, determine whether the TEE is permitted to program the requested DMA channel. The computing device may record the TEE for a request to protect the DMA channel and may determine whether the programming TEE matches the recorded TEE for a request to unprotect a DMA channel. The computing device may allow the request to unprotect the DMA channel if the programming TEE matches the recorded TEE. Other embodiments are described and claimed.

摘要翻译： 用于加密引擎的安全编程的技术包括具有密码引擎和一个或多个I / O控制器的计算设备。 计算设备建立一个或多个可信执行环境（TEE）。 TEE生成关于DMA通道对加密引擎进行编程的请求。 计算设备可以验证指示允许编程DMA通道的TEE的签名清单，并且如果被验证，则确定是否允许TEE对所请求的DMA通道进行编程。 计算设备可以记录TEE以保护DMA通道的请求，并且可以确定编程TEE是否与用于取消保护DMA通道的请求的记录的TEE匹配。 如果编程TEE与记录的TEE匹配，则计算设备可以允许请求取消对DMA通道的保护。 描述和要求保护其他实施例。

公开(公告)号：US09501668B2

公开(公告)日：2016-11-22

申请号：US14036263

申请日：2013-09-25

申请人： Siddhartha Chhabra ,  Uday R. Savagaonkar ,  Prashant Dewan ,  David M. Durham ,  Balaji Vembu ,  Xiaozhu Kang ,  Scott Janus ,  Jason Martin ,  Vincent R. Scarlata

发明人： Siddhartha Chhabra ,  Uday R. Savagaonkar ,  Prashant Dewan ,  David M. Durham ,  Balaji Vembu ,  Xiaozhu Kang ,  Scott Janus ,  Jason Martin ,  Vincent R. Scarlata

IPC分类号： H04N7/167 ,  G06F21/82 ,  G06F21/84 ,  G06F21/85 ,  H04N21/41 ,  H04N21/4143 ,  H04N21/4367

CPC分类号： G06F21/82 ,  G06F21/84 ,  G06F21/85 ,  H04N21/4122 ,  H04N21/4143 ,  H04N21/4367

摘要： Systems and methods for secure delivery of output surface bitmaps to a display engine. An example processing system comprises: an architecturally protected memory; and a processing core communicatively coupled to the architecturally protected memory, the processing core comprising a processing logic configured to implement an architecturally-protected execution environment by performing at least one of: executing instructions residing in the architecturally protected memory and preventing an unauthorized access to the architecturally protected memory; wherein the processing logic is further configured to provide a secure video output path by generating an output surface bitmap encrypted with a first encryption key and storing an encrypted first encryption key in an external memory, wherein the encrypted first encryption key is produced by encrypting the first encryption key with a second encryption key.

摘要翻译： 用于将输出表面位图安全传递到显示引擎的系统和方法。 一个示例处理系统包括：架构受保护的存储器; 以及处理核心，其通信地耦合到所述体系结构保护的存储器，所述处理核心包括处理逻辑，所述处理逻辑被配置为通过执行以下中的至少一个来实现架构保护的执行环境：执行驻留在所述体系结构保护的存储器中的指令， 建筑保护记忆; 其中所述处理逻辑还被配置为通过生成用第一加密密钥加密并将加密的第一加密密钥存储在外部存储器中的输出表面位图来提供安全视频输出路径，其中所述加密的第一加密密钥是通过加密所述第一加密密钥 具有第二加密密钥的加密密钥。

公开(公告)号：US20150089173A1

公开(公告)日：2015-03-26

申请号：US14034813

申请日：2013-09-24

申请人： Siddhartha Chhabra ,  Uday R. Savagaonkar ,  Michael A. Goldsmith ,  Simon P. Johnson ,  Rebekah M. Leslie-Hurd ,  Francis X. McKeen ,  Gilbert Neiger ,  Raghunandan Makaram ,  Carlos V. Rozas ,  Amy L. Santoni ,  Vincent R. Scarlata ,  Vedvyas Shanbhogue ,  Wesley H. Smith ,  Ittai Anati ,  Ilya Alexandrovich

发明人： Siddhartha Chhabra ,  Uday R. Savagaonkar ,  Michael A. Goldsmith ,  Simon P. Johnson ,  Rebekah M. Leslie-Hurd ,  Francis X. McKeen ,  Gilbert Neiger ,  Raghunandan Makaram ,  Carlos V. Rozas ,  Amy L. Santoni ,  Vincent R. Scarlata ,  Vedvyas Shanbhogue ,  Wesley H. Smith ,  Ittai Anati ,  Ilya Alexandrovich

IPC分类号： G06F12/14 ,  G06F12/08

CPC分类号： G06F12/1408 ,  G06F9/45558 ,  G06F12/0808 ,  G06F12/0897 ,  G06F12/1027 ,  G06F2009/45587 ,  G06F2212/1032 ,  G06F2212/1048 ,  G06F2212/152

摘要： Secure memory repartitioning technologies are described. A processor includes a processor core and a memory controller coupled between the processor core and main memory. The main memory includes a memory range including a section of convertible pages are convertible to secure pages or non-secure pages. The processor core, in response to a page conversion instruction, is to determine from the instruction a convertible page in the memory range to be converted and convert the convertible page to be at least one of a secure page or a non-secure page. The memory range may also include a hardware reserved section are convertible in response to a section conversion instruction.

摘要翻译： 描述了安全的内存重新分区技术。 处理器包括耦合在处理器核心和主存储器之间的处理器核心和存储器控制器。 主存储器包括一个内存范围，包括可转换页面的一部分可转换为安全页面或非安全页面。 响应于页面转换指令的处理器核心是从指令中确定要转换的存储器范围内的可转换页面，并将可转换页面转换为安全页面或非安全页面中的至少一个页面。 存储器范围还可以包括可响应于段转换指令而转换的硬件保留部分。

公开(公告)号：US20140173756A1

公开(公告)日：2014-06-19

申请号：US13719907

申请日：2012-12-19

申请人： Siddhartha Chhabra ,  Reshma Lal

发明人： Siddhartha Chhabra ,  Reshma Lal

IPC分类号： G06F21/10

CPC分类号： G06F21/10 ,  H04L9/0825 ,  H04L9/32 ,  H04L63/08

摘要： Embodiments of an invention for platform-hardened digital rights management key provisioning are disclosed. In one embodiment, a processor includes an execution unit to execute one or more instructions to create a secure enclave in which to run an application to receive digital rights management information from a provisioning server in response to authentication of the application by a verification server.

摘要翻译： 公开了用于平台硬化的数字版权管理密钥提供的发明的实施例。 在一个实施例中，处理器包括执行单元，用于执行一个或多个指令以创建安全空间，其中响应于验证服务器对应用的认证，运行应用以从供应服务器接收数字版权管理信息。

公开(公告)号：US20150086012A1

公开(公告)日：2015-03-26

申请号：US14036263

申请日：2013-09-25

申请人： Siddhartha Chhabra ,  Uday R. Savagaonkar ,  Prashant Dewan ,  David M. Durham ,  Balaji Vembu ,  Xiaozhu Kang ,  Scott Janus ,  Jason Martin ,  Vincent R. Scarlata

发明人： Siddhartha Chhabra ,  Uday R. Savagaonkar ,  Prashant Dewan ,  David M. Durham ,  Balaji Vembu ,  Xiaozhu Kang ,  Scott Janus ,  Jason Martin ,  Vincent R. Scarlata

IPC分类号： H04N7/167

CPC分类号： G06F21/82 ,  G06F21/84 ,  G06F21/85 ,  H04N21/4122 ,  H04N21/4143 ,  H04N21/4367

摘要： Systems and methods for secure delivery of output surface bitmaps to a display engine. An example processing system comprises: an architecturally protected memory; and a processing core communicatively coupled to the architecturally protected memory, the processing core comprising a processing logic configured to implement an architecturally-protected execution environment by performing at least one of: executing instructions residing in the architecturally protected memory and preventing an unauthorized access to the architecturally protected memory; wherein the processing logic is further configured to provide a secure video output path by generating an output surface bitmap encrypted with a first encryption key and storing an encrypted first encryption key in an external memory, wherein the encrypted first encryption key is produced by encrypting the first encryption key with a second encryption key.

摘要翻译： 用于将输出表面位图安全传递到显示引擎的系统和方法。 一个示例处理系统包括：架构受保护的存储器; 以及处理核心，其通信地耦合到所述体系结构保护的存储器，所述处理核心包括处理逻辑，所述处理逻辑被配置为通过执行以下中的至少一个来实现架构保护的执行环境：执行驻留在架构保护的存储器中的指令， 建筑保护记忆; 其中所述处理逻辑还被配置为通过生成用第一加密密钥加密并将加密的第一加密密钥存储在外部存储器中的输出表面位图来提供安全视频输出路径，其中所述加密的第一加密密钥是通过加密所述第一加密密钥 具有第二加密密钥的加密密钥。

公开(公告)号：US20140157404A1

公开(公告)日：2014-06-05

申请号：US13690111

申请日：2012-11-30

申请人： Siddhartha Chhabra ,  Reshma Lal ,  Jason Martin ,  Daniel Nemiroff

发明人： Siddhartha Chhabra ,  Reshma Lal ,  Jason Martin ,  Daniel Nemiroff

IPC分类号： G06F21/50

CPC分类号： G06F21/50 ,  G06F21/54 ,  G06F21/71

摘要： Embodiments of an invention for virtualizing a hardware monotonic counter are disclosed. In one embodiment, an apparatus includes a hardware monotonic counter, virtualization logic, a first non-volatile storage location, and a second non-volatile storage location. The virtualization logic is to create a virtual monotonic counter from the hardware monotonic counter. The first non-volatile storage location is to store an indicator that the count of the hardware monotonic counter has changed. The second non-volatile storage location is to store an indicator that the count of the virtual monotonic counter has changed.

摘要翻译： 公开了用于虚拟化硬件单调计数器的发明的实施例。 在一个实施例中，装置包括硬件单调计数器，虚拟化逻辑，第一非易失性存储位置和第二非易失性存储位置。 虚拟化逻辑是从硬件单调计数器创建一个虚拟单调计数器。 第一个非易失性存储位置是存储硬件单调计数器的计数改变的指示符。 第二非易失性存储位置是存储虚拟单调计数器的计数改变的指示符。

公开(公告)号：US20210409209A1

公开(公告)日：2021-12-30

申请号：US16913283

申请日：2020-06-26

申请人： Siddhartha Chhabra ,  HORMUZD M. KHOSRAVI

发明人： Siddhartha Chhabra ,  HORMUZD M. KHOSRAVI

IPC分类号： H04L9/08 ,  G06F3/06 ,  G06F9/4401

摘要： An apparatus includes a processor, persistent memory coupled to the processor, and a memory protection logic. The processor may include multiple processing engines. The persistent memory may include a persistent storage portion and a memory expansion portion. The memory protection logic is to: obtain a first ephemeral component associated with the persistent storage portion; generate a persistent key using the first ephemeral component; obtain a second ephemeral component associated with the memory expansion portion; and generate a non-persistent key using the second ephemeral component. Other embodiments are described and claimed.