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    Power shifting in multicore platforms by varying SMT levels
    3.
    发明授权
    Power shifting in multicore platforms by varying SMT levels 有权
    通过改变SMT级别在多核平台中进行功率转换

    公开(公告)号：US09043626B2

    公开(公告)日：2015-05-26

    申请号：US13529161

    申请日：2012-06-21

    申请人： Pradip Bose ,  Alper Buyuktosunoglu ,  Dilma Menezes Da Silva ,  Hubertus Franke ,  Priyanka Tembey

    发明人： Pradip Bose ,  Alper Buyuktosunoglu ,  Dilma Menezes Da Silva ,  Hubertus Franke ,  Priyanka Tembey

    IPC分类号： G06F1/32 ,  G06F9/50

    CPC分类号： G06F1/3206 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/329 ,  G06F9/4893 ,  G06F9/50 ,  Y02D10/24

    摘要： Power consumption in a microprocessor platform is managed by setting a peak power level for power consumed by a multi-core microprocessor platform executing multi-threaded applications. The multi-core microprocessor platform contains a plurality of physical cores, and each physical core is configurable into a plurality of logical cores. A simultaneous multithreading level in at least one physical core is adjusted by changing the number of logical cores on that physical core in response to a power consumption level of the multi-core microprocessor platform exceeding the peak power level. Performance and power data based on simultaneous multi-threading levels are used in selecting the physical core to be adjusted.

    摘要翻译： 通过设置执行多线程应用程序的多核微处理器平台消耗的功耗的峰值功率级别来管理微处理器平台中的功耗。 多核微处理器平台包含多个物理核，每个物理核可配置成多个逻辑核。 响应于多核微处理器平台的功率消耗水平超过峰值功率水平，通过改变该物理核心上的逻辑核心数来调整至少一个物理核心中的同时多线程级别。 基于同步多线程级别的性能和功耗数据用于选择要调整的物理内核。

    ADAPTIVE WORKLOAD BASED OPTIMIZATIONS COUPLED WITH A HETEROGENEOUS CURRENT-AWARE BASELINE DESIGN TO MITIGATE CURRENT DELIVERY LIMITATIONS IN INTEGRATED CIRCUITS
    5.
    发明申请
    ADAPTIVE WORKLOAD BASED OPTIMIZATIONS COUPLED WITH A HETEROGENEOUS CURRENT-AWARE BASELINE DESIGN TO MITIGATE CURRENT DELIVERY LIMITATIONS IN INTEGRATED CIRCUITS 有权
    基于自适应工作负载的优化与异构电流基准设计相结合，以减轻集成电路中的电流传输限制

    公开(公告)号：US20140195996A1

    公开(公告)日：2014-07-10

    申请号：US13526252

    申请日：2012-06-18

    申请人： Pradip Bose ,  Alper Buyuktosunoglu ,  John A. Darringer ,  Moinuddin K. Qureshi ,  Jeonghee Shin

    发明人： Pradip Bose ,  Alper Buyuktosunoglu ,  John A. Darringer ,  Moinuddin K. Qureshi ,  Jeonghee Shin

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072 ,  G06F17/5036

    摘要： A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.

    摘要翻译： 与“前置硅”设计方法和“后硅”当前优化编程方法相结合的动态系统，以改进和优化当前传输到芯片的传输，这受到连接的物理特性的限制（例如，受控崩溃芯片连接或 C4s）。 该机制包括测量或估计芯片内特定粒度的功耗，使用一种方法将功率信息转换为C4当前信息，并在适用的情况下触发限流机制（包括基于令牌的限制），以限制每个C4超过预先的当前传输 - 建立的限制或期限。 设计辅助工具用于根据当前交付要求在整个芯片上分配C4。 该系统与设计和编程方法相结合，改进并优化电流传递可扩展到多层3D芯片堆叠中的层间连接。

    Token-Based Current Control to Mitigate Current Delivery Limitations in Integrated Circuits
    6.
    发明申请
    Token-Based Current Control to Mitigate Current Delivery Limitations in Integrated Circuits 有权
    基于令牌的电流控制，以缓解集成电路中的当前传输限制

    公开(公告)号：US20140082574A1

    公开(公告)日：2014-03-20

    申请号：US13526153

    申请日：2012-06-18

    申请人： Pradip Bose ,  Alper Buyuktosunoglu ,  John A. Darringer ,  Moinuddin K. Qureshi ,  Jeonghee Shin

    发明人： Pradip Bose ,  Alper Buyuktosunoglu ,  John A. Darringer ,  Moinuddin K. Qureshi ,  Jeonghee Shin

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054 ,  G06F9/455 ,  G06F9/46 ,  G06F9/5044 ,  G06F15/177 ,  G06F17/5022 ,  G06F17/5045 ,  G06F2212/1041 ,  G06F2217/78

    摘要： A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.

    摘要翻译： 与“前置硅”设计方法和“后硅”当前优化编程方法相结合的动态系统，以改进和优化当前传输到芯片的传输，这受到连接的物理特性的限制（例如，受控崩溃芯片连接或 C4s）。 该机制包括测量或估计芯片内特定粒度的功耗，使用一种方法将功率信息转换为C4当前信息，并在适用的情况下触发限流机制（包括基于令牌的限制），以限制每个C4超过预先的当前传输 - 建立的限制或期限。 设计辅助工具用于根据当前交付要求在整个芯片上分配C4。 该系统与设计和编程方法相结合，改进并优化电流传递可扩展到多层3D芯片堆叠中的层间连接。

    Dynamically tune power proxy architectures
    7.
    发明授权
    Dynamically tune power proxy architectures 有权
    动态调优电源代理架构

    公开(公告)号：US08635483B2

    公开(公告)日：2014-01-21

    申请号：US13079842

    申请日：2011-04-05

    申请人： Emrah Acar ,  Pradip Bose ,  Bishop C. Brock ,  Alper Buyuktosunoglu ,  Michael S. Floyd ,  Maria L. Pesantez ,  Gregory S. Still

    发明人： Emrah Acar ,  Pradip Bose ,  Bishop C. Brock ,  Alper Buyuktosunoglu ,  Michael S. Floyd ,  Maria L. Pesantez ,  Gregory S. Still

    IPC分类号： G06F1/00 ,  G06F1/26 ,  G06F15/00 ,  G01R21/00 ,  G01R19/00

    CPC分类号： G06F1/3243 ,  Y02D10/152

    摘要： A mechanism is provided for automatically tuning power proxy architectures. Based on the set of conditions related to an application being executed on a microprocessor core, a weight factor to use for each activity in a set of activities being monitored for the microprocessor core is identified, thereby forming a set of weight factors. A power usage estimate value is generated using the set of activities and the set of weight factors. A determination is made as to whether the power usage estimate value is greater than a power proxy threshold value identifying a maximum power usage for the microprocessor core. Responsive to the power usage estimate value being greater than the power proxy threshold value, a set of signals is sent to one or more on-chip actuators in the power proxy unit associated with the microprocessor core and a set of operational parameters associated with the component are adjusted.

    摘要翻译： 提供了一种自动调整电源代理架构的机制。 基于与在微处理器核心上执行的应用有关的条件集合，识别用于针对微处理器核心的一组活动中的每个活动的权重因子，从而形成一组权重因子。 使用一组活动和一组权重因子生成用电量估计值。 确定功率使用估计值是否大于识别微处理器核的最大功率使用的功率代理阈值。 响应于功率使用估计值大于功率代理阈值，一组信号被发送到与微处理器核心相关联的功率代理单元中的一个或多个片上致动器，以及与组件相关联的一组操作参数 被调整。

    Guarded, multi-metric resource control for safe and efficient microprocessor management
    8.
    发明授权
    Guarded, multi-metric resource control for safe and efficient microprocessor management 失效
    保护，多度量资源控制，用于安全高效的微处理器管理

    公开(公告)号：US08527994B2

    公开(公告)日：2013-09-03

    申请号：US13024781

    申请日：2011-02-10

    申请人： Pradip Bose ,  Alper Buyuktosunoglu ,  Niti Madan

    发明人： Pradip Bose ,  Alper Buyuktosunoglu ,  Niti Madan

    IPC分类号： G06F9/46

    CPC分类号： G06F11/3058 ,  G06F1/3206 ,  G06F1/3234 ,  G06F9/5094 ,  Y02D10/22

    摘要： A mechanism is provided for guarded, multi-metric resource control. Monitoring is performed for an intended action to address a negative condition from a resource manager in a plurality of resource managers in the data processing system. Responsive to receiving the intended action, a determination is made as to whether the intended action will cause an additional negative condition within the data processing system. Responsive to determining that the intended action will cause the additional negative condition within the data processing system, at least one alternative action is identified to be implemented in the data processing system that addresses the negative condition while not causing any additional negative condition. The at least one alternative action is then implemented in the data processing system.

    摘要翻译： 提供了一种用于保护的多度量资源控制的机制。 执行针对数据处理系统中的多个资源管理器中的资源管理器处理负面条件的预期动作的监视。 响应于接收预期的动作，确定预期动作是否将在数据处理系统内引起额外的负面情况。 响应于确定预期动作将导致数据处理系统内的附加负面条件，至少一个备选动作被识别为在不引起任何附加负面条件的情况下处理负条件的数据处理系统中实现。 然后在数据处理系统中实现至少一个备选动作。

    Method and system of multi-core microprocessor power management and control via per-chiplet, programmable power modes
    9.
    发明授权
    Method and system of multi-core microprocessor power management and control via per-chiplet, programmable power modes 有权
    多核微处理器的功能管理和控制方法和系统，通过每小时可编程电源模式进行

    公开(公告)号：US08001394B2

    公开(公告)日：2011-08-16

    申请号：US12023536

    申请日：2008-01-31

    申请人： Pradip Bose ,  Alper Buyuktosunoglu ,  Michael Stephen Floyd

    发明人： Pradip Bose ,  Alper Buyuktosunoglu ,  Michael Stephen Floyd

    IPC分类号： G06F1/26 ,  G06F1/32

    CPC分类号： G06F1/3203 ,  G06F1/3243 ,  G06F1/3287 ,  Y02D10/152 ,  Y02D10/171

    摘要： A computer-implemented method and a system for managing power in a multi-core microprocessor are provided. A power management control microarchitecture in a chiplet translates a first command comprising a power setting. A chiplet comprises a processor core and associated memory cache. The power management control microarchitecture comprises power mode registers, power mode adjusters, translators, and microarchitectural power management techniques. The power management control microarchitecture sets microarchitectural power management techniques according to the power setting. The global power management controller issues the first command. The global power management controller may reside either on or off of the microprocessor. The global power management controller issues commands either directly for a specific chiplet out of the plurality of chiplets or to the plurality of chiplets and the control slave bus translates the command into sub-commands dedicated to specific chiplets within the plurality of chiplets. Each chiplet may be set to separate power levels.

    摘要翻译： 提供了一种计算机实现的方法和用于管理多核微处理器中的电力的系统。 小电流中的电源管理控制微体系结构转换包括功率设置的第一命令。 小巧包括处理器核心和相关联的存储器高速缓存。 功率管理控制微体系结构包括功率模式寄存器，功率模式调节器，转换器和微架构电源管理技术。 电源管理控制微架构根据功率设置设置微体系结构电源管理技术。 全球电源管理控制器发出第一个命令。 全局功率管理控制器可以驻留在微处理器上或者关闭。 全局功率管理控制器直接针对多个小芯片中的特定小时或多个小芯片发出命令，并且控制从总线将命令转换为专用于多个小芯片内的特定小芯片的子命令。 每个小穗可以设置为分开的功率水平。

    Two-Level Guarded Predictive Power Gating
    10.
    发明申请
    Two-Level Guarded Predictive Power Gating 有权
    两级保护预测电源门控

    公开(公告)号：US20110040994A1

    公开(公告)日：2011-02-17

    申请号：US12539941

    申请日：2009-08-12

    申请人： Jayanta Basak ,  Pradip Bose ,  Alper Buyuktosunoglu ,  Anita Lungu

    发明人： Jayanta Basak ,  Pradip Bose ,  Alper Buyuktosunoglu ,  Anita Lungu

    IPC分类号： G06F1/26

    CPC分类号： G06F1/3203 ,  G06F11/3466 ,  Y02D10/34

    摘要： A mechanism is provided for two-level guarded predictive power gating of a set of units within the data processing system. A success determines whether a unit within the set of units is power gated during a monitoring interval. If the unit is power gated, the success monitor determines whether a count of idle cycles for the unit is below a breakeven point. If the count is above the breakeven point, the success monitor increments a success efficiency counter. If the count is below the breakeven point, the success monitor determines whether the unit needs to be woke up. If the unit needs to be woke up, the success monitor increments a harmful efficiency counter. If the value of the harmful efficiency counter is less than the value from the success efficiency counter, the success monitor enables power gating for the unit via a first-level power-gating mechanism.

    摘要翻译： 提供了一种用于数据处理系统内的一组单元的两级保护预测能力门控的机制。 一个成功的确定在一个监视间隔期间该单元组内的一个单元是否电源门控。 如果该单元是电源门控，则成功监视器确定该单元的空闲周期计数是否低于盈亏平衡点。 如果计数高于盈亏平衡点，则成功监视器会增加成功效率计数器。 如果计数低于盈亏平衡点，则成功监视器确定该单元是否需要醒来。 如果单位需要醒来，成功监测器会增加一个有害的效率计数器。 如果有害效率计数器的值小于成功效率计数器的值，则成功监视器可通过一级电源门控机构对单元进行功率门控。