公开(公告)号：US07800420B2

公开(公告)日：2010-09-21

申请号：US12346900

申请日：2008-12-31

Applicant: Pankaj Kumar ,  Pramod Elamannu Parameswaran ,  Anuroop Iyengar ,  Vani Deshpande

Inventor： Pankaj Kumar ,  Pramod Elamannu Parameswaran ,  Anuroop Iyengar ,  Vani Deshpande

IPC: H03L7/00

CPC classification number: H03K17/223

Abstract: A power detect system and circuit for detecting a voltage level of an input/output supply voltage (VDDIO) in a circuit of low voltage devices is disclosed. In one embodiment, the power detect system and circuit includes a voltage divider coupled between the VDDIO and a negative supply voltage (VSS) for generating a bias voltage, a first inverter coupled between a core voltage (VDD) and the VSS for generating a first node voltage based on the bias voltage, a native device coupled between the VDDIO and the VSS for generating a second node voltage based on the bias voltage, and a switch coupled between the first inverter and the native device for controlling the second node voltage based on the first node voltage. The power detect system further includes a second inverter coupled between the VDD and the VSS for generating an output voltage based on the second node voltage.

Abstract translation: 公开了一种用于检测低压器件的电路中的输入/输出电源电压（VDDIO）的电压电平的功率检测系统和电路。 在一个实施例中，功率检测系统和电路包括耦合在VDDIO和用于产生偏置电压的负电源电压（VSS）之间的分压器，耦合在核心电压（VDD）和VSS之间的第一反相器，用于产生第一 基于所述偏置电压的节点电压，耦合在所述VDDIO和所述VSS之间以产生基于所述偏置电压的第二节点电压的本机装置，以及耦合在所述第一反相器和所述本机装置之间的开关，用于基于 第一节点电压。 功率检测系统还包括耦合在VDD和VSS之间的第二反相器，用于基于第二节点电压产生输出电压。

公开(公告)号：US20100026342A1

公开(公告)日：2010-02-04

申请号：US12185073

申请日：2008-08-02

Applicant: PRAMOD ELAMANNU PARAMESWARAN ,  Pankaj Kumar

Inventor： PRAMOD ELAMANNU PARAMESWARAN ,  Pankaj Kumar

IPC: H03K19/0175

CPC classification number: H03K19/018528

Abstract: A high voltage input receiver using low voltage transistors is disclosed. In one embodiment, an input receiver circuit includes a comparator circuit and an inverter circuit. The comparator circuit includes a differential input module for generating a control signal by comparing an external voltage and a reference voltage, and a decision module for generating an inverter input signal based on the control signal. In addition, the reference voltage is used to set dc trip point of the input receiver. Moreover, the input receiver includes one or more stress protection modules to protect key components of the input receiver from exceeding their reliability limits.

Abstract translation: 公开了一种使用低压晶体管的高压输入接收器。 在一个实施例中，输入接收器电路包括比较器电路和反相器电路。 比较器电路包括用于通过比较外部电压和参考电压来产生控制信号的差分输入模块和用于基于控制信号产生反相器输入信号的判定模块。 此外，参考电压用于设置输入接收器的直流跳变点。 此外，输入接收器包括一个或多个应力保护模块，用于保护输入接收器的关键部件不超出其可靠性限制。

公开(公告)号：US07821327B2

公开(公告)日：2010-10-26

申请号：US12185073

申请日：2008-08-02

Applicant: Pramod Elamannu Parameswaran ,  Pankaj Kumar

Inventor： Pramod Elamannu Parameswaran ,  Pankaj Kumar

IPC: G05F1/10 ,  H03K3/356

CPC classification number: H03K19/018528

Abstract: A high voltage input receiver using low voltage transistors is disclosed. In one embodiment, an input receiver circuit includes a comparator circuit and an inverter circuit. The comparator circuit includes a differential input module for generating a control signal by comparing an external voltage and a reference voltage, and a decision module for generating an inverter input signal based on the control signal. In addition, the reference voltage is used to set dc trip point of the input receiver. Moreover, the input receiver includes one or more stress protection modules to protect key components of the input receiver from exceeding their reliability limits.

Abstract translation: 公开了一种使用低压晶体管的高压输入接收器。 在一个实施例中，输入接收器电路包括比较器电路和反相器电路。 比较器电路包括用于通过比较外部电压和参考电压来产生控制信号的差分输入模块和用于基于控制信号产生反相器输入信号的判定模块。 此外，参考电压用于设置输入接收器的直流跳变点。 此外，输入接收器包括一个或多个应力保护模块，用于保护输入接收器的关键部件不超出其可靠性限制。

公开(公告)号：US08482329B2

公开(公告)日：2013-07-09

申请号：US12188227

申请日：2008-08-08

Applicant: Vani Deshpande ,  Anuroop Iyengar ,  Pramod Elamannu Parameswaran ,  Pankaj Kumar

Inventor： Vani Deshpande ,  Anuroop Iyengar ,  Pramod Elamannu Parameswaran ,  Pankaj Kumar

IPC: H03K3/00

CPC classification number: H03K5/2481 ,  H03K3/3565

Abstract: A high voltage input receiver with hysteresis using low voltage transistors is disclosed. In one embodiment, an input receiver circuit includes a hysteresis comparator circuit, based on a plurality of low voltage transistors, for generating a first output voltage by comparing an external voltage and a reference voltage and a stress protection circuit for preventing the plurality of low voltage transistors of the hysteresis comparator circuit from exceeding their reliability limits. In addition, the reference voltage is used to set a positive trip point and a negative trip point. Moreover, the input receiver circuit includes a source follower circuit for transferring the first output voltage to an output node of the source follower circuit from a voltage level of a VDDIO to a voltage level of a VDD.

Abstract translation: 公开了一种使用低压晶体管的具有滞后的高压输入接收器。 在一个实施例中，输入接收器电路包括基于多个低压晶体管的滞后比较器电路，用于通过比较外部电压和参考电压产生第一输出电压，以及用于防止多个低电压的应力保护电路 迟滞比较器电路的晶体管超过其可靠性限制。 此外，参考电压用于设置正跳变点和负跳变点。 此外，输入接收器电路包括源极跟随器电路，用于将源极跟随器电路的输出节点的第一输出电压从VDDIO的电压电平转换到VDD的电压电平。

公开(公告)号：US07902904B2

公开(公告)日：2011-03-08

申请号：US12330828

申请日：2008-12-09

Applicant: Pankaj Kumar ,  Makeshwar Kothandaraman ,  Dipankar Bhattacharya ,  John Kriz ,  Jeffrey J. Nagy ,  Pramod Elamannu Parameswaran

Inventor： Pankaj Kumar ,  Makeshwar Kothandaraman ,  Dipankar Bhattacharya ,  John Kriz ,  Jeffrey J. Nagy ,  Pramod Elamannu Parameswaran

IPC: G05F1/10

CPC classification number: G05F3/16

Abstract: Disclosed is a bias circuit with a first resistor connected between the supply voltage and a feedback node. Resistors are connected in series between the feedback node and the reference supply voltage. The connections between the resistors define at least one bias voltage. A second resistor is connected between the feedback node and a first drain node. A first field-effect transistor has a first gate node, the first drain node, and a first source node. The gate node is connected to the first supply voltage. A second field-effect transistor has a second gate node, a second drain node, and a second source node. The second drain node is connected to the first source node. The second gate node is connected to the bias voltage. The second source node is connected to an output signal node. The output signal node capable of experiencing an overshoot voltage.

Abstract translation: 公开了一种偏置电路，其中第一电阻器连接在电源电压和反馈节点之间。 电阻器连接在反馈节点和参考电源电压之间。 电阻之间的连接限定了至少一个偏置电压。 第二电阻器连接在反馈节点和第一漏极节点之间。 第一场效应晶体管具有第一栅极节点，第一漏极节点和第一源节点。 门节点连接到第一电源电压。 第二场效应晶体管具有第二栅极节点，第二漏极节点和第二源节点。 第二排水节点连接到第一源节点。 第二栅极节点连接到偏置电压。 第二源节点连接到输出信号节点。 输出信号节点能够经历过冲电压。

公开(公告)号：US20110102048A1

公开(公告)日：2011-05-05

申请号：US12889440

申请日：2010-09-24

Applicant: Pankaj Kumar ,  Pramod Elamannu Parameswaran ,  Makeshwar Kothandaraman ,  Vani Deshpande ,  John Kriz

Inventor： Pankaj Kumar ,  Pramod Elamannu Parameswaran ,  Makeshwar Kothandaraman ,  Vani Deshpande ,  John Kriz

IPC: H03L5/00

CPC classification number: H03K19/00315

Abstract: A method includes controllably generating a first bias voltage from a supply voltage to be within an upper tolerable limit of an operating voltage of one or more constituent active circuit element(s) of an Input/Output (IO) core device of an integrated circuit (IC) to be interfaced with an IO pad, and controllably generating a second bias voltage from an external voltage supplied through the IO pad to be within the upper tolerable limit of the operating voltage of the one or more constituent active circuit element(s) of the IO core device to be interfaced with the IO pad. The method also includes controllably utilizing a control signal generated by the IO core to derive an output bias voltage from the first bias voltage during a driver mode of operation or the second bias voltage during a failsafe mode of operation and a tolerant mode of operation.

Abstract translation: 一种方法包括可控制地从电源电压产生第一偏置电压，使其处于集成电路的输入/输出（IO）核心器件的一个或多个构成的有源电路元件的工作电压的上容许限度内（ IC）与IO焊盘接口，并且可控制地从通过IO焊盘提供的外部电压产生第二偏置电压，使其在所述一个或多个构成的有源电路元件的工作电压的上容许限度内 要与IO接口连接的IO内核设备。 该方法还包括可控制地利用由IO核心产生的控制信号，以在驱动器操作模式期间从第一偏置电压导出输出偏置电压，或者在故障安全操作模式和容限操作模式期间导出第二偏置电压。

公开(公告)号：US07876132B1

公开(公告)日：2011-01-25

申请号：US12580280

申请日：2009-10-16

Applicant: Pankaj Kumar ,  Pramod Elamannu Parameswaran ,  Makeshwar Kothandaraman ,  Vani Deshpande ,  John Kriz

Inventor： Pankaj Kumar ,  Pramod Elamannu Parameswaran ,  Makeshwar Kothandaraman ,  Vani Deshpande ,  John Kriz

IPC: H03B1/00

CPC classification number: H03K17/08104 ,  H03K17/063 ,  H03K19/00315 ,  H03K2217/0018

Abstract: A circuit includes a first comparator block configured to output a voltage equal to a higher of a supply voltage and a bias voltage, a second comparator block configured to output a voltage equal to a higher of the bias voltage and an external voltage supplied through an Input/Output (IO) pad, and a third comparator block configured to output a voltage equal to a higher of the output of the first comparator block and the output of the second comparator block. A voltage across one or more constituent active element(s) of each of the first comparator block, the second comparator block, and the third comparator block is within an upper tolerable limit thereof during each of a normal operation, a failsafe operation, and a tolerant operation.

Abstract translation: 电路包括：第一比较器块，被配置为输出等于较高的电源电压和偏置电压的电压;第二比较器块，被配置为输出等于较高偏置电压的电压和通过输入提供的外部电压 /输出（IO）焊盘和第三比较器块，其被配置为输出等于第一比较器块的输出的较高的电压和第二比较器块的输出。 第一比较器块，第二比较器块和第三比较器块中的每个的一个或多个构成有源元件上的电压在正常操作，故障安全操作和 容忍操作。

公开(公告)号：US20100164591A1

公开(公告)日：2010-07-01

申请号：US12346900

申请日：2008-12-31

Applicant: Pankaj Kumar ,  Pramod Elamannu Parameswaran ,  Anuroop Iyengar ,  Vani Deshpande

Inventor： Pankaj Kumar ,  Pramod Elamannu Parameswaran ,  Anuroop Iyengar ,  Vani Deshpande

IPC: H03L5/00

CPC classification number: H03K17/223

Abstract: A power detect system and circuit for detecting a voltage level of an input/output supply voltage (VDDIO) in a circuit of low voltage devices is disclosed. In one embodiment, the power detect system and circuit includes a voltage divider coupled between the VDDIO and a negative supply voltage (VSS) for generating a bias voltage, a first inverter coupled between a core voltage (VDD) and the VSS for generating a first node voltage based on the bias voltage, a native device coupled between the VDDIO and the VSS for generating a second node voltage based on the bias voltage, and a switch coupled between the first inverter and the native device for controlling the second node voltage based on the first node voltage. The power detect system further includes a second inverter coupled between the VDD and the VSS for generating an output voltage based on the second node voltage.

Abstract translation: 公开了一种用于检测低压器件的电路中的输入/输出电源电压（VDDIO）的电压电平的功率检测系统和电路。 在一个实施例中，功率检测系统和电路包括耦合在VDDIO和用于产生偏置电压的负电源电压（VSS）之间的分压器，耦合在核心电压（VDD）和VSS之间的第一反相器，用于产生第一 基于所述偏置电压的节点电压，耦合在所述VDDIO和所述VSS之间以产生基于所述偏置电压的第二节点电压的本机装置，以及耦合在所述第一反相器和所述本机装置之间的开关，用于基于 第一节点电压。 功率检测系统还包括耦合在VDD和VSS之间的第二反相器，用于基于第二节点电压产生输出电压。

公开(公告)号：US20100141334A1

公开(公告)日：2010-06-10

申请号：US12330828

申请日：2008-12-09

Applicant: Pankaj Kumar ,  Makeshwar Kothandaraman ,  Dipankar Bhattacharya ,  John Kriz ,  Jeffrey J. Nagy ,  Pramod Elamannu Parameswaran

Inventor： Pankaj Kumar ,  Makeshwar Kothandaraman ,  Dipankar Bhattacharya ,  John Kriz ,  Jeffrey J. Nagy ,  Pramod Elamannu Parameswaran

IPC: G05F1/10

CPC classification number: G05F3/16

Abstract: Disclosed is a bias circuit with a first resistor connected between the supply voltage and a feedback node. Resistors are connected in series between the feedback node and the reference supply voltage. The connections between the resistors define at least one bias voltage. A second resistor is connected between the feedback node and a first drain node. A first field-effect transistor has a first gate node, the first drain node, and a first source node. The gate node is connected to the first supply voltage. A second field-effect transistor has a second gate node, a second drain node, and a second source node. The second drain node is connected to the first source node. The second gate node is connected to the bias voltage. The second source node is connected to an output signal node. The output signal node capable of experiencing an overshoot voltage.

Abstract translation: 公开了一种偏置电路，其中第一电阻器连接在电源电压和反馈节点之间。 电阻器连接在反馈节点和参考电源电压之间。 电阻之间的连接限定了至少一个偏置电压。 第二电阻器连接在反馈节点和第一漏极节点之间。 第一场效应晶体管具有第一栅极节点，第一漏极节点和第一源节点。 门节点连接到第一电源电压。 第二场效应晶体管具有第二栅极节点，第二漏极节点和第二源节点。 第二排水节点连接到第一源节点。 第二栅极节点连接到偏置电压。 第二源节点连接到输出信号节点。 输出信号节点能够经历过冲电压。

公开(公告)号：US20100033214A1

公开(公告)日：2010-02-11

申请号：US12188227

申请日：2008-08-08

Applicant: Vani Deshpande ,  Anuroop Iyengar ,  Pramod Elamannu Parameswaran ,  Pankaj Kumar

Inventor： Vani Deshpande ,  Anuroop Iyengar ,  Pramod Elamannu Parameswaran ,  Pankaj Kumar

IPC: H03K5/24

CPC classification number: H03K5/2481 ,  H03K3/3565

Abstract: A high voltage input receiver with hysteresis using low voltage transistors is disclosed. In one embodiment, an input receiver circuit includes a hysteresis comparator circuit, based on a plurality of low voltage transistors, for generating a first output voltage by comparing an external voltage and a reference voltage and a stress protection circuit for preventing the plurality of low voltage transistors of the hysteresis comparator circuit from exceeding their reliability limits. In addition, the reference voltage is used to set a positive trip point and a negative trip point. Moreover, the input receiver circuit includes a source follower circuit for transferring the first output voltage to an output node of the source follower circuit from a voltage level of a VDDIO to a voltage level of a VDD.

Abstract translation: 公开了一种使用低压晶体管的具有滞后的高压输入接收器。 在一个实施例中，输入接收器电路包括基于多个低压晶体管的滞后比较器电路，用于通过比较外部电压和参考电压产生第一输出电压，以及用于防止多个低电压的应力保护电路 迟滞比较器电路的晶体管超过其可靠性限制。 此外，参考电压用于设置正跳变点和负跳变点。 此外，输入接收器电路包括源极跟随器电路，用于将源极跟随器电路的输出节点的第一输出电压从VDDIO的电压电平转换到VDD的电压电平。