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公开(公告)号：US08199779B2
公开(公告)日：2012-06-12
申请号：US13021627
申请日：2011-02-04
申请人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Eli Arviv
发明人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Eli Arviv
摘要： Apparatus, system and method for synchronizing one or more clocks across a communication link. A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave side. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate which is related as n times the slave clock rate. The synchronization signal receipt time indicated by the correlation sample sequence may be refined by interpolating the correlation sample sequence around a best correlation sample to locate a best interpolation at an interpolation resolution smaller than the sample resolution. The best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output. The synchronization signal receipt time thus determined is compared to the expected time based upon the slave clock, which is adjusted until the times match. After initialization, all slave clock errors are preferably accumulated to prevent long-term slip between the slave and master clocks. Formerly independent master and slave clocks synchronized across the communication link constitute a noncommon clock which may be compared on each side of the link to secondary independent clocks, and the secondary independent clocks may then be separately synchronized by adjusting one to have the same difference from its local noncommon clock as the secondary clock on the other side of the link has from its local noncommon clock.
摘要翻译： 用于在通信链路上同步一个或多个时钟的装置，系统和方法。 从时钟可以通过从主机发送到链路的从时钟侧的同步信号与主时钟同步。 同步信号可以是以从机侧预期的间隔发送的预期信号模式。 从时钟可以将接收的信号与预期同步信号的表示相关，以产生与从时钟速率的n倍相关的第一采样率的相关采样序列。 通过相关采样序列指示的同步信号接收时间可以通过围绕最佳相关样本内插相关采样序列来精细化，以便以小于样本分辨率的插值分辨率定位最佳内插。 可以通过在与最佳内插输出相邻的内插器输出之间进行估计来进一步改进最佳内插。 将这样确定的同步信号接收时间与基于从时钟的预期时间进行比较，该从时钟被调整直到时间匹配。 在初始化之后，优选地累积所有从时钟错误以防止从机和主时钟之间的长期滑动。 通过通信链路同步的以前独立的主，从时钟构成了一个非常见的时钟，可以在链路的每一侧与次级独立时钟进行比较，然后可以通过调整二次独立时钟来与其独立时钟相同的差异 本地非通用时钟作为链路另一侧的辅助时钟源自其本地非通用时钟。
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公开(公告)号：US07583705B2
公开(公告)日：2009-09-01
申请号：US11170391
申请日：2005-06-29
申请人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Eli Arviv
发明人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Eli Arviv
摘要： One or more clocks are synchronized across a communication link using a synchronization signal sent from a master to a slave clock. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate. The synchronization signal receipt time is compared to the expected time and the slave clock is adjusted until the times match. Master and slave clocks synchronized across the communication link constitute a noncommon clock which may be compared on each side of the link to secondary independent clocks. The secondary independent clocks may be separately synchronized by adjusting one to have the same difference from its local noncommon clock as the secondary clock on the other side of the link has from its local noncommon clock.
摘要翻译： 使用从主机发送到从时钟的同步信号，通过通信链路同步一个或多个时钟。 同步信号可以是以从站所预期的间隔发送的预期信号模式。 从时钟可以将接收的信号与预期同步信号的表示相关，以产生第一采样率的相关采样序列。 将同步信号接收时间与预期时间进行比较，并调整从时钟直到时间匹配。 通过通信链路同步的主和从时钟构成了一个非常见的时钟，可以在链路的每一侧与次级独立时钟进行比较。 辅助独立时钟可以通过调整一个来独立同步，以使其与本地非常见时钟具有相同的差异，因为链路另一侧的辅助时钟与其本地非常见时钟相同。
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公开(公告)号：US20110122981A1
公开(公告)日：2011-05-26
申请号：US13021627
申请日：2011-02-04
申请人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Eli Arviv
发明人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Eli Arviv
IPC分类号： H04L7/00
摘要： Apparatus, system and method for synchronizing one or more clocks across a communication link. A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave side. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate which is related as n times the slave clock rate. The synchronization signal receipt time indicated by the correlation sample sequence may be refined by interpolating the correlation sample sequence around a best correlation sample to locate a best interpolation at an interpolation resolution smaller than the sample resolution. The best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output. The synchronization signal receipt time thus determined is compared to the expected time based upon the slave clock, which is adjusted until the times match. After initialization, all slave clock errors are preferably accumulated to prevent long-term slip between the slave and master clocks. Formerly independent master and slave clocks synchronized across the communication link constitute a noncommon clock which may be compared on each side of the link to secondary independent clocks, and the secondary independent clocks may then be separately synchronized by adjusting one to have the same difference from its local noncommon clock as the secondary clock on the other side of the link has from its local noncommon clock.
摘要翻译： 用于在通信链路上同步一个或多个时钟的装置，系统和方法。 从时钟可以通过从主机发送到链路的从时钟侧的同步信号与主时钟同步。 同步信号可以是以从机侧预期的间隔发送的预期信号模式。 从时钟可以将接收的信号与预期同步信号的表示相关，以产生与从时钟速率的n倍相关的第一采样率的相关采样序列。 通过相关采样序列指示的同步信号接收时间可以通过围绕最佳相关样本内插相关采样序列来精细化，以便以小于样本分辨率的插值分辨率定位最佳内插。 可以通过在与最佳内插输出相邻的内插器输出之间进行估计来进一步改进最佳内插。 将这样确定的同步信号接收时间与基于从时钟的预期时间进行比较，该从时钟被调整直到时间匹配。 在初始化之后，优选地累积所有从时钟错误以防止从机和主时钟之间的长期滑动。 通过通信链路同步的以前独立的主，从时钟构成了一个非常见的时钟，可以在链路的每一侧与次级独立时钟进行比较，然后可以通过调整二次独立时钟来与其独立时钟相同的差异 本地非通用时钟作为链路另一侧的辅助时钟源自其本地非通用时钟。
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公开(公告)号：US07907640B2
公开(公告)日：2011-03-15
申请号：US12508431
申请日：2009-07-23
申请人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Eli Arviv
发明人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Eli Arviv
摘要： A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave side. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate which is related as n times the slave clock rate. A best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output. The synchronization signal receipt time thus determined is compared to the expected time based upon the slave clock, which is adjusted until the times match. The best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output.
摘要翻译： 从时钟可以通过从主机发送到链路的从时钟侧的同步信号与主时钟同步。 同步信号可以是以从机侧预期的间隔发送的预期信号模式。 从时钟可以将接收的信号与预期同步信号的表示相关，以产生与从时钟速率的n倍相关的第一采样率的相关采样序列。 可以通过在与最佳内插输出相邻的内插器输出之间进行估计来进一步改进最佳内插。 将这样确定的同步信号接收时间与基于从时钟的预期时间进行比较，该从时钟被调整直到时间匹配。 可以通过在与最佳内插输出相邻的内插器输出之间进行估计来进一步改进最佳内插。
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公开(公告)号：US20090279652A1
公开(公告)日：2009-11-12
申请号：US12508431
申请日：2009-07-23
申请人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Eli Arviv
发明人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Eli Arviv
IPC分类号： H04L7/00
摘要： Apparatus, system and method for synchronizing one or more clocks across a communication link. A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave side. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate which is related as n times the slave clock rate. The synchronization signal receipt time indicated by the correlation sample sequence may be refined by interpolating the correlation sample sequence around a best correlation sample to locate a best interpolation at an interpolation resolution smaller than the sample resolution. The best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output. The synchronization signal receipt time thus determined is compared to the expected time based upon the slave clock, which is adjusted until the times match. After initialization, all slave clock errors are preferably accumulated to prevent long-term slip between the slave and master clocks. Formerly independent master and slave clocks synchronized across the communication link constitute a noncommon clock which may be compared on each side of the link to secondary independent clocks, and the secondary independent clocks may then be separately synchronized by adjusting one to have the same difference from its local noncommon clock as the secondary clock on the other side of the link has from its local noncommon clock.
摘要翻译： 用于在通信链路上同步一个或多个时钟的装置，系统和方法。 从时钟可以通过从主机发送到链路的从时钟侧的同步信号与主时钟同步。 同步信号可以是以从机侧预期的间隔发送的预期信号模式。 从时钟可以将接收的信号与预期同步信号的表示相关，以产生与从时钟速率的n倍相关的第一采样率的相关采样序列。 通过相关采样序列指示的同步信号接收时间可以通过围绕最佳相关样本内插相关采样序列来精细化，以便以小于样本分辨率的插值分辨率定位最佳内插。 可以通过在与最佳内插输出相邻的内插器输出之间进行估计来进一步改进最佳内插。 将这样确定的同步信号接收时间与基于从时钟的预期时间进行比较，该从时钟被调整直到时间匹配。 在初始化之后，优选地累积所有从时钟错误以防止从机和主时钟之间的长期滑动。 通过通信链路同步的以前独立的主，从时钟构成了一个非常见的时钟，可以在链路的每一侧与次级独立时钟进行比较，然后可以通过调整二次独立时钟来与其独立时钟相同的差异 本地非通用时钟作为链路另一侧的辅助时钟源自其本地非通用时钟。
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公开(公告)号：US06944188B2
公开(公告)日：2005-09-13
申请号：US09790443
申请日：2001-02-21
申请人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Ell Arviv
发明人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Ell Arviv
摘要： Apparatus, system and method for synchronizing one or more clocks across a communication link. A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave side. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate which is related as n times the slave clock rate. The synchronization signal receipt time indicated by the correlation sample sequence may be refined by interpolating the correlation sample sequence around a best correlation sample to locate a best interpolation at an interpolation resolution smaller than the sample resolution. The best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output. The synchronization signal receipt time thus determined is compared to the expected time based upon the slave clock, which is adjusted until the times match. After initialization, all slave clock errors are preferably accumulated to prevent long-term slip between the slave and master clocks. Formerly independent master and slave clocks synchronized across the communication link constitute a noncommon clock which may be compared on each side of the link to secondary independent clocks, and the secondary independent clocks may then be separately synchronized by adjusting one to have the same difference from its local noncommon clock as the secondary clock on the other side of the link has from its local noncommon clock.
摘要翻译： 用于在通信链路上同步一个或多个时钟的装置，系统和方法。 从时钟可以通过从主机发送到链路的从时钟侧的同步信号与主时钟同步。 同步信号可以是以从机侧预期的间隔发送的预期信号模式。 从时钟可以将接收的信号与预期同步信号的表示相关，以产生与从时钟速率的n倍相关的第一采样率的相关采样序列。 通过相关采样序列指示的同步信号接收时间可以通过围绕最佳相关样本内插相关采样序列来精细化，以便以小于样本分辨率的插值分辨率来定位最佳内插。 可以通过在与最佳内插输出相邻的内插器输出之间进行估计来进一步改进最佳内插。 将这样确定的同步信号接收时间与基于从时钟的预期时间进行比较，该从时钟被调整直到时间匹配。 在初始化之后，优选地累积所有从时钟错误以防止从机和主时钟之间的长期滑动。 通过通信链路同步的以前独立的主，从时钟构成了一个非常见的时钟，可以在链路的每一侧与次级独立时钟进行比较，然后可以通过调整二次独立时钟来与其独立时钟相同的差异 本地非通用时钟作为链路另一侧的辅助时钟源自其本地非通用时钟。
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公开(公告)号：US20070002987A1
公开(公告)日：2007-01-04
申请号：US11170391
申请日：2005-06-29
申请人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Gallagher , Sheldon Gilbert , Stephen Pollmann , Frederick Price , Blaine Readler , John Wiss , Eli Arviv
发明人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Gallagher , Sheldon Gilbert , Stephen Pollmann , Frederick Price , Blaine Readler , John Wiss , Eli Arviv
IPC分类号： H04L7/00
摘要： Apparatus, system and method for synchronizing one or more clocks across a communication link. A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave side. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate which is related as n times the slave clock rate. The synchronization signal receipt time indicated by the correlation sample sequence may be refined by interpolating the correlation sample sequence around a best correlation sample to locate a best interpolation at an interpolation resolution smaller than the sample resolution. The best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output. The synchronization signal receipt time thus determined is compared to the expected time based upon the slave clock, which is adjusted until the times match. After initialization, all slave clock errors are preferably accumulated to prevent long-term slip between the slave and master clocks. Formerly independent master and slave clocks synchronized across the communication link constitute a noncommon clock which may be compared on each side of the link to secondary independent clocks, and the secondary independent clocks may then be separately synchronized by adjusting one to have the same difference from its local noncommon clock as the secondary clock on the other side of the link has from its local noncommon clock.
摘要翻译： 用于在通信链路上同步一个或多个时钟的装置，系统和方法。 从时钟可以通过从主机发送到链路的从时钟侧的同步信号与主时钟同步。 同步信号可以是以从机侧预期的间隔发送的预期信号模式。 从时钟可以将接收的信号与预期同步信号的表示相关，以产生与从时钟速率的n倍相关的第一采样率的相关采样序列。 通过相关采样序列指示的同步信号接收时间可以通过围绕最佳相关样本内插相关采样序列来精细化，以便以小于样本分辨率的插值分辨率定位最佳内插。 可以通过在与最佳内插输出相邻的内插器输出之间进行估计来进一步改进最佳内插。 将这样确定的同步信号接收时间与基于从时钟的预期时间进行比较，该从时钟被调整直到时间匹配。 在初始化之后，优选地累积所有从时钟错误以防止从机和主时钟之间的长期滑动。 通过通信链路同步的以前独立的主，从时钟构成了一个非常见的时钟，可以在链路的每一侧与次级独立时钟进行比较，然后可以通过调整二次独立时钟来与其独立时钟相同的差异 本地非通用时钟作为链路另一侧的辅助时钟源自其本地非通用时钟。
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公开(公告)号：US5737693A
公开(公告)日：1998-04-07
申请号：US582741
申请日：1996-01-04
CPC分类号： H01L23/3107 , H01L23/3121 , H01L23/3128 , H04B17/16 , H04B17/29 , H01L2924/0002
摘要： A baseband simulation system is disclosed for testing an RF subsystem of a communication device, such as a cellular telephone, cordless telephone, etc. A preferred embodiment has a computer connected to an interface card which in turn is connected to a baseband simulation subsystem. The baseband simulation subsystem is connected to the RF subsystem under test. The baseband simulation subsystem includes three ports: a timing and control (TAC) port, an IQ port, and general purpose input output (GPIO) port. The TAC port receives a master clock signal from an external source and generates plural clocks therefrom. The IQ and GPIO ports receives at least one of these plural clocks. In a transmit mode, in response to one or more of the clocks generated by the TAC port, the IQ port retrieves from its memory prestored discrete I and Q samples and reconstructs therefrom arbitrary transmit analog i and q signals which are provided to the RF subsystem under test. In a receive mode, the IQ port receives analog i and q signals from the RF subsystem. The IQ port, in response to one or more clocks generated by the TAC port, converts the received analog i and q signals receive discrete I and Q samples. These receive discrete I and Q samples are transferred via the PCIF to the PC for analyzing the ability of the RF subsystem under test to modulate the inputted transmit analog i and q signals on one or more RF carrier signals and to demodulate the RF carrier signals to output the receive analog i and q signals. The GPIO port exchanges auxiliary discrete data with the PC and auxiliary analog signals with the RF subsystem under test.
摘要翻译： 公开了用于测试诸如蜂窝电话，无绳电话等的通信设备的RF子系统的基带模拟系统。优选实施例具有连接到接口卡的计算机，该接口卡又连接到基带模拟子系统。 基带仿真子系统连接到正在测试的RF子系统。 基带模拟子系统包括三个端口：定时和控制（TAC）端口，IQ端口和通用输入输出（GPIO）端口。 TAC端口从外部源接收主时钟信号并从其产生多个时钟信号。 IQ和GPIO端口至少接收到一个这些多个时钟。 在发送模式中，响应于由TAC端口产生的时钟中的一个或多个时钟，IQ端口从其存储器中检索预存储的离散I和Q采样，并从其中重构提供给RF子系统的任意发射模拟i和q信号 被测试。 在接收模式下，IQ端口从RF子系统接收模拟i和q信号。 IQ端口响应于由TAC端口产生的一个或多个时钟，转换所接收的模拟i和q信号接收离散的I和Q采样。 这些接收离散的I和Q样本通过PCIF传送到PC，用于分析被测RF射频子系统在一个或多个RF载波信号上调制输入的发射模拟i和q信号的能力，并将RF载波信号解调为 输出接收模拟i和q信号。 GPIO端口与PC和辅助模拟信号交换辅助离散数据，并与RF子系统进行测试。
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9.发明授权Soft trellis slicer for improving the performance of a decision-directed phase tracker 有权软网格切片机，用于提高决策型相位跟踪器的性能公开(公告)号：US06882690B1
公开(公告)日：2005-04-19
申请号：US09668231
申请日：2000-09-22
CPC分类号： H04L25/03318 , H04L1/0054 , H04L1/0057 , H04L1/006 , H04L1/0065 , H04L1/0071 , H04L25/03197 , H04L27/06 , H04L2027/0057
摘要： A soft trellis slicer is provided in a high definition television (HDTV) receiver. The soft trellis slicer calculates a decision value and a confidence value corresponding to a phase angle error of a signal processed by the receiver. The receiver includes an equalizer, a phase tracking loop and a trellis decoder. The equalizer provides an equalized signal to the phase tracking loop; and the phase tracking loop calculates a phase angle error for the equalized signal. The trellis decoder calculates a decision value and a confidence value. The trellis decoder provides the decision value and the confidence value to the phase tracking loop, which calculates the reliability of the phase angle error based upon the phase angle error and the decision value and the confidence value provided by the trellis decoder. The trellis decoder calculates the decision value based upon a best path metric and calculates the confidence value based upon the best path metric and a second best path metric.
摘要翻译： 在高分辨率电视（HDTV）接收机中提供了软网格切片机。 软网格切片机计算与由接收机处理的信号的相位角误差相对应的判定值和置信度值。 接收机包括均衡器，相位跟踪环和网格解码器。 均衡器向相位跟踪环路提供均衡信号; 相位跟踪环计算均衡信号的相位角误差。 网格解码器计算决策值和置信度值。 网格解码器向相位跟踪环路提供决策值和置信度值，该相位跟踪环路根据相位角误差和网格解码器提供的判定值和置信度值来计算相位角误差的可靠性。 网格解码器基于最佳路径度量来计算决策值，并且基于最佳路径量度和第二最佳路径量度来计算置信度值。
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10.发明授权Multiple clock generation in a baseband simulator for testing a radio frequency section of a mobile communications transceiver 失效用于测试移动通信收发器的射频部分的基带模拟器中的多时钟生成
公开(公告)号：US5887244A
公开(公告)日：1999-03-23
申请号：US582742
申请日：1996-01-04
IPC分类号： H04B17/00
摘要： A baseband simulation system is disclosed for testing an RF subsystem of a communication device, such as a cellular telephone, cordless telephone, etc. A preferred embodiment has a computer connected to an interface card which in turn is connected to a baseband simulation subsystem. The baseband simulation subsystem is connected to the RF subsystem under test. The baseband simulation subsystem includes three ports: a timing and control (TAC) port, an IQ port, and general purpose input output (GPIO) port. The TAC port receives a master clock signal from an external source and generates plural clocks therefrom. The IQ and GPIO ports receives at least one of these plural clocks. In a transmit mode, in response to one or more of the clocks generated by the TAC port, the IQ port retrieves from its memory prestored discrete I and Q samples and reconstructs therefrom arbitrary transmit analog i and q signals which are provided to the RF subsystem under test. In a receive mode, the IQ port receives analog i and q signals from the RF subsystem. The IQ port, in response to one or more clocks generated by the TAC port, converts the received analog i and q signals receive discrete I and Q samples. These receive discrete I and Q samples are transferred via the PCIF to the PC for analyzing the ability of the RF subsystem under test to modulate the inputted transmit analog i and q signals on one or more RF carrier signals and to demodulate the RF carrier signals to output the receive analog i and q signals. The GPIO port exchanges auxiliary discrete data with the PC and auxiliary analog signals with the RF subsystem under test.
摘要翻译： 公开了用于测试诸如蜂窝电话，无绳电话等的通信设备的RF子系统的基带模拟系统。优选实施例具有连接到接口卡的计算机，该接口卡又连接到基带模拟子系统。 基带仿真子系统连接到正在测试的RF子系统。 基带模拟子系统包括三个端口：定时和控制（TAC）端口，IQ端口和通用输入输出（GPIO）端口。 TAC端口从外部源接收主时钟信号并从其产生多个时钟信号。 IQ和GPIO端口至少接收到一个这些多个时钟。 在发送模式中，响应于由TAC端口产生的时钟中的一个或多个时钟，IQ端口从其存储器中检索预存储的离散I和Q采样，并从其中重构提供给RF子系统的任意发射模拟i和q信号 被测试。 在接收模式下，IQ端口从RF子系统接收模拟i和q信号。 IQ端口响应于由TAC端口产生的一个或多个时钟，转换所接收的模拟i和q信号接收离散的I和Q采样。 这些接收离散的I和Q样本通过PCIF传送到PC，用于分析被测RF射频子系统在一个或多个RF载波信号上调制输入的发射模拟i和q信号的能力，并将RF载波信号解调为 输出接收模拟i和q信号。 GPIO端口与PC和辅助模拟信号交换辅助离散数据，并与RF子系统进行测试。
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