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公开(公告)号：US20110122981A1
公开(公告)日：2011-05-26
申请号：US13021627
申请日：2011-02-04
申请人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Eli Arviv
发明人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Eli Arviv
IPC分类号： H04L7/00
摘要： Apparatus, system and method for synchronizing one or more clocks across a communication link. A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave side. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate which is related as n times the slave clock rate. The synchronization signal receipt time indicated by the correlation sample sequence may be refined by interpolating the correlation sample sequence around a best correlation sample to locate a best interpolation at an interpolation resolution smaller than the sample resolution. The best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output. The synchronization signal receipt time thus determined is compared to the expected time based upon the slave clock, which is adjusted until the times match. After initialization, all slave clock errors are preferably accumulated to prevent long-term slip between the slave and master clocks. Formerly independent master and slave clocks synchronized across the communication link constitute a noncommon clock which may be compared on each side of the link to secondary independent clocks, and the secondary independent clocks may then be separately synchronized by adjusting one to have the same difference from its local noncommon clock as the secondary clock on the other side of the link has from its local noncommon clock.
摘要翻译： 用于在通信链路上同步一个或多个时钟的装置，系统和方法。 从时钟可以通过从主机发送到链路的从时钟侧的同步信号与主时钟同步。 同步信号可以是以从机侧预期的间隔发送的预期信号模式。 从时钟可以将接收的信号与预期同步信号的表示相关，以产生与从时钟速率的n倍相关的第一采样率的相关采样序列。 通过相关采样序列指示的同步信号接收时间可以通过围绕最佳相关样本内插相关采样序列来精细化，以便以小于样本分辨率的插值分辨率定位最佳内插。 可以通过在与最佳内插输出相邻的内插器输出之间进行估计来进一步改进最佳内插。 将这样确定的同步信号接收时间与基于从时钟的预期时间进行比较，该从时钟被调整直到时间匹配。 在初始化之后，优选地累积所有从时钟错误以防止从机和主时钟之间的长期滑动。 通过通信链路同步的以前独立的主，从时钟构成了一个非常见的时钟，可以在链路的每一侧与次级独立时钟进行比较，然后可以通过调整二次独立时钟来与其独立时钟相同的差异 本地非通用时钟作为链路另一侧的辅助时钟源自其本地非通用时钟。
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公开(公告)号：US07907640B2
公开(公告)日：2011-03-15
申请号：US12508431
申请日：2009-07-23
申请人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Eli Arviv
发明人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Eli Arviv
摘要： A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave side. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate which is related as n times the slave clock rate. A best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output. The synchronization signal receipt time thus determined is compared to the expected time based upon the slave clock, which is adjusted until the times match. The best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output.
摘要翻译： 从时钟可以通过从主机发送到链路的从时钟侧的同步信号与主时钟同步。 同步信号可以是以从机侧预期的间隔发送的预期信号模式。 从时钟可以将接收的信号与预期同步信号的表示相关，以产生与从时钟速率的n倍相关的第一采样率的相关采样序列。 可以通过在与最佳内插输出相邻的内插器输出之间进行估计来进一步改进最佳内插。 将这样确定的同步信号接收时间与基于从时钟的预期时间进行比较，该从时钟被调整直到时间匹配。 可以通过在与最佳内插输出相邻的内插器输出之间进行估计来进一步改进最佳内插。
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公开(公告)号：US20090279652A1
公开(公告)日：2009-11-12
申请号：US12508431
申请日：2009-07-23
申请人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Eli Arviv
发明人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Eli Arviv
IPC分类号： H04L7/00
摘要： Apparatus, system and method for synchronizing one or more clocks across a communication link. A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave side. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate which is related as n times the slave clock rate. The synchronization signal receipt time indicated by the correlation sample sequence may be refined by interpolating the correlation sample sequence around a best correlation sample to locate a best interpolation at an interpolation resolution smaller than the sample resolution. The best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output. The synchronization signal receipt time thus determined is compared to the expected time based upon the slave clock, which is adjusted until the times match. After initialization, all slave clock errors are preferably accumulated to prevent long-term slip between the slave and master clocks. Formerly independent master and slave clocks synchronized across the communication link constitute a noncommon clock which may be compared on each side of the link to secondary independent clocks, and the secondary independent clocks may then be separately synchronized by adjusting one to have the same difference from its local noncommon clock as the secondary clock on the other side of the link has from its local noncommon clock.
摘要翻译： 用于在通信链路上同步一个或多个时钟的装置，系统和方法。 从时钟可以通过从主机发送到链路的从时钟侧的同步信号与主时钟同步。 同步信号可以是以从机侧预期的间隔发送的预期信号模式。 从时钟可以将接收的信号与预期同步信号的表示相关，以产生与从时钟速率的n倍相关的第一采样率的相关采样序列。 通过相关采样序列指示的同步信号接收时间可以通过围绕最佳相关样本内插相关采样序列来精细化，以便以小于样本分辨率的插值分辨率定位最佳内插。 可以通过在与最佳内插输出相邻的内插器输出之间进行估计来进一步改进最佳内插。 将这样确定的同步信号接收时间与基于从时钟的预期时间进行比较，该从时钟被调整直到时间匹配。 在初始化之后，优选地累积所有从时钟错误以防止从机和主时钟之间的长期滑动。 通过通信链路同步的以前独立的主，从时钟构成了一个非常见的时钟，可以在链路的每一侧与次级独立时钟进行比较，然后可以通过调整二次独立时钟来与其独立时钟相同的差异 本地非通用时钟作为链路另一侧的辅助时钟源自其本地非通用时钟。
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公开(公告)号：US20050058098A1
公开(公告)日：2005-03-17
申请号：US10962957
申请日：2004-10-12
申请人： Israel Klein , Kenneth Stanwood , Steve Pollmann , Frederick Price , Rami Hadar , Eli Arviv , David Gazelle , Sheldon Gilbert
发明人： Israel Klein , Kenneth Stanwood , Steve Pollmann , Frederick Price , Rami Hadar , Eli Arviv , David Gazelle , Sheldon Gilbert
CPC分类号： H04B7/2656 , H04L1/0003 , H04L1/0004 , H04L1/0057 , H04L1/0059 , H04L1/0065 , H04L1/0083 , H04L25/03038 , H04L27/0008 , H04L2025/0342 , H04L2025/03477 , H04W72/0446 , H04W88/02 , H04W88/08 , Y02D50/10
摘要： A method of assigning downlink time slots to receive units where the units may generate data using different modulation schemes. The method preferably assigns the downlink time slots as a function of the complexity of modulation schemes employed by the units. Further, the method preferably assigns the time slots from the least complex modulation scheme to the most complex scheme. The method may further assign uplink time slots to transmit units where the transmit units may generate data using different modulation schemes. The method preferably assigns the uplink time slots as a function of the complexity of modulation schemes employed by the uplink units. Further, the method preferably assigns the uplink time slots from the least complex modulation scheme to the most complex scheme. In other embodiments, the downlink time slots are assigned as a function of the bit per symbol rate employed by the receive units, preferably from the lowest bit per symbol rate to the highest bit per symbol rate. Further, the uplink time slots are assigned as a function of the bit per symbol rate employed by the transmit units, preferably from the lowest bit per symbol rate to the highest bit per symbol rate. The present invention is also a method of simplifying the encoding of a predetermined number of bits of data into frames. The method adds error coding bits so that a ratio of the frame length times the baud rate of the frame times the bit packing ratio of the data divided the total bits of data is always an integer. The method may also convolutionally encode the bits of data so that the same equation is also always an integer. The present invention is also a method of updating the weights of a FIR filter where the filter processes symbols having variable modulation rates. When the modulation rate of the incoming symbols changes, the weights corresponding to the first symbol having the new modulation rate are changed based as the symbol propagates through the filter.
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公开(公告)号：US08199779B2
公开(公告)日：2012-06-12
申请号：US13021627
申请日：2011-02-04
申请人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Eli Arviv
发明人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Eli Arviv
摘要： Apparatus, system and method for synchronizing one or more clocks across a communication link. A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave side. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate which is related as n times the slave clock rate. The synchronization signal receipt time indicated by the correlation sample sequence may be refined by interpolating the correlation sample sequence around a best correlation sample to locate a best interpolation at an interpolation resolution smaller than the sample resolution. The best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output. The synchronization signal receipt time thus determined is compared to the expected time based upon the slave clock, which is adjusted until the times match. After initialization, all slave clock errors are preferably accumulated to prevent long-term slip between the slave and master clocks. Formerly independent master and slave clocks synchronized across the communication link constitute a noncommon clock which may be compared on each side of the link to secondary independent clocks, and the secondary independent clocks may then be separately synchronized by adjusting one to have the same difference from its local noncommon clock as the secondary clock on the other side of the link has from its local noncommon clock.
摘要翻译： 用于在通信链路上同步一个或多个时钟的装置，系统和方法。 从时钟可以通过从主机发送到链路的从时钟侧的同步信号与主时钟同步。 同步信号可以是以从机侧预期的间隔发送的预期信号模式。 从时钟可以将接收的信号与预期同步信号的表示相关，以产生与从时钟速率的n倍相关的第一采样率的相关采样序列。 通过相关采样序列指示的同步信号接收时间可以通过围绕最佳相关样本内插相关采样序列来精细化，以便以小于样本分辨率的插值分辨率定位最佳内插。 可以通过在与最佳内插输出相邻的内插器输出之间进行估计来进一步改进最佳内插。 将这样确定的同步信号接收时间与基于从时钟的预期时间进行比较，该从时钟被调整直到时间匹配。 在初始化之后，优选地累积所有从时钟错误以防止从机和主时钟之间的长期滑动。 通过通信链路同步的以前独立的主，从时钟构成了一个非常见的时钟，可以在链路的每一侧与次级独立时钟进行比较，然后可以通过调整二次独立时钟来与其独立时钟相同的差异 本地非通用时钟作为链路另一侧的辅助时钟源自其本地非通用时钟。
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公开(公告)号：US08130640B2
公开(公告)日：2012-03-06
申请号：US12395347
申请日：2009-02-27
申请人： Israel Jay Klein , Kenneth L. Stanwood , Steve Pollmann , Frederick W. Price , Rami Hadar , Eli Arviv , David Gazelle , Sheldon Gilbert
发明人： Israel Jay Klein , Kenneth L. Stanwood , Steve Pollmann , Frederick W. Price , Rami Hadar , Eli Arviv , David Gazelle , Sheldon Gilbert
IPC分类号： H04J1/16
CPC分类号： H04B7/2656 , H04L1/0003 , H04L1/0004 , H04L1/0057 , H04L1/0059 , H04L1/0065 , H04L1/0083 , H04L25/03038 , H04L27/0008 , H04L2025/0342 , H04L2025/03477 , H04W72/0446 , H04W88/02 , H04W88/08 , Y02D50/10
摘要： A method of simplifying the encoding of a predetermined number of bits of data into frames including adding error coding bits so that a ratio of the frame length times the baud rate of the frame times he bit packing ratio of the data divided the total bits of data is always an integer. The method may also convolutionally encode the bits of data so that the same equation is also always an integer.
摘要翻译： 一种将预定数量的数据位的编码简化为帧的方法，该帧包括相加错误编码位，使得帧长度乘以帧的比特率乘以数据的比特打包率乘以数据的总比特数 总是一个整数。 该方法还可以对数据的比特进行卷积编码，使得相同的方程也总是为整数。
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公开(公告)号：US07583705B2
公开(公告)日：2009-09-01
申请号：US11170391
申请日：2005-06-29
申请人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Eli Arviv
发明人： Pranesh Sinha , Sharon Akler , Yair Bourlas , Timothy Leo Gallagher , Sheldon L. Gilbert , Stephen C. Pollmann , Frederick W. Price , Blaine C. Readler , John Wiss , Eli Arviv
摘要： One or more clocks are synchronized across a communication link using a synchronization signal sent from a master to a slave clock. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate. The synchronization signal receipt time is compared to the expected time and the slave clock is adjusted until the times match. Master and slave clocks synchronized across the communication link constitute a noncommon clock which may be compared on each side of the link to secondary independent clocks. The secondary independent clocks may be separately synchronized by adjusting one to have the same difference from its local noncommon clock as the secondary clock on the other side of the link has from its local noncommon clock.
摘要翻译： 使用从主机发送到从时钟的同步信号，通过通信链路同步一个或多个时钟。 同步信号可以是以从站所预期的间隔发送的预期信号模式。 从时钟可以将接收的信号与预期同步信号的表示相关，以产生第一采样率的相关采样序列。 将同步信号接收时间与预期时间进行比较，并调整从时钟直到时间匹配。 通过通信链路同步的主和从时钟构成了一个非常见的时钟，可以在链路的每一侧与次级独立时钟进行比较。 辅助独立时钟可以通过调整一个来独立同步，以使其与本地非常见时钟具有相同的差异，因为链路另一侧的辅助时钟与其本地非常见时钟相同。
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公开(公告)号：US06597733B2
公开(公告)日：2003-07-22
申请号：US09800268
申请日：2001-03-05
申请人： Stephen C. Pollmann , Eli Arviv , Jacques Behar , Timothy L. Gallagher , David Gazelle , Frederick W. Price
发明人： Stephen C. Pollmann , Eli Arviv , Jacques Behar , Timothy L. Gallagher , David Gazelle , Frederick W. Price
IPC分类号： H04B138
CPC分类号： H04L1/20 , H04L1/0003 , H04L1/0036 , H04L1/004 , H04L7/0029 , H04L7/042 , H04L25/03057 , H04L27/0012 , H04L27/3809 , H04L2025/03401 , H04L2025/0342 , H04L2025/03668 , H04L2025/03783
摘要： A system and method for enhancing the performance of an equalizer in a modem. Multiple techniques are disclosed which improve the modem performance. A first technique uses stored parameters for each burst from each remote site to demodulate a received data stream. A second technique compensates for the gain droop caused by storing parameters across each burst. A third technique minimizes errors caused by adapting the equalizer coefficients for each data burst by analyzing the SN ratio and error rate of the received burst. A fourth technique improves the convergence of the equalizer by using a two-part preamble, whereby both parts are transmitted using different modulation techniques. A fifth technique is provided which performs a soft reset of the modem without performing a complete reset of the modem. A sixth technique determines a modem adaptation factor based on the expected modulation type of an incoming burst transmission. A seventh technique calculates a phase correction value for the stored tap values and applies the value to the incoming signal.
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公开(公告)号：US5960360A
公开(公告)日：1999-09-28
申请号：US941127
申请日：1997-09-29
申请人： Rafael Carmon , Mark Shahaf , Eli Arviv
发明人： Rafael Carmon , Mark Shahaf , Eli Arviv
摘要： A communication method is provided in which mobiles operating in a trunk mode operation transmit a message on a direct mode operation channel indicating a trunk mode operation connection is present. If a mobile outside the range of coverage of the trunking system receives the message it will deduce from the message the slot structure of the trunk mode channel and its timing, and will then be able to transmit a request for a direct mode connection on an appropriate slot of the trunk mode channel. Some or all of the mobiles operating in trunk mode will then be able to switch to direct mode to connect with the mobile outside the range of coverage.
摘要翻译： 提供一种通信方法，其中以中继模式操作的移动台在指示中继线模式操作连接的直接模式操作信道上发送消息。 如果在中继系统的覆盖范围之外的移动台接收到消息，则该消息将从消息中推断中继线模式信道的时隙结构及其定时，并且然后将能够以适当的方式发送对直接模式连接的请求 中继线模式通道的插槽。 在干线模式下运行的部分或全部手机将能够切换到直接模式以在覆盖范围之外与移动设备进行连接。
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公开(公告)号：USRE42021E1
公开(公告)日：2011-01-04
申请号：US11187034
申请日：2005-07-20
申请人： Stephen C. Pollmann , Eli Arviv , Jacques Behar , Timothy L. Gallagher , David Gazelle , Frederick W. Price
发明人： Stephen C. Pollmann , Eli Arviv , Jacques Behar , Timothy L. Gallagher , David Gazelle , Frederick W. Price
CPC分类号： H04L1/20 , H04L1/0003 , H04L1/0036 , H04L1/004 , H04L7/0029 , H04L7/042 , H04L25/03057 , H04L27/0012 , H04L27/3809 , H04L2025/03401 , H04L2025/0342 , H04L2025/03668 , H04L2025/03783
摘要： A system and method for enhancing the performance of an equalizer in a modem. Multiple techniques are disclosed which improve the modem performance. A first technique uses stored parameters for each burst from each remote site to demodulate a received data stream. A second technique compensates for the gain droop caused by storing parameters across each burst. A third technique minimizes errors caused by adapting the equalizer coefficients for each data burst by analyzing the SN ratio and error rate of the received burst. A fourth technique improves the convergence of the equalizer by using a two-part preamble, whereby both parts are transmitted using different modulation techniques. A fifth technique is provided which performs a soft reset of the modem without performing a complete reset of the modem. A sixth technique determines a modem adaptation factor based on the expected modulation type of an incoming burst transmission. A seventh technique calculates a phase correction value for the stored tap values and applies the value to the incoming signal.
摘要翻译： 一种用于增强调制解调器中的均衡器的性能的系统和方法。 公开了改进调制解调器性能的多种技术。 第一种技术使用来自每个远程站点的每个突发的存储参数来解调所接收的数据流。 第二种技术补偿了通过在每个突发之间存储参数而引起的增益下降。 第三种技术通过分析接收到的突发的SN比和错误率来最小化通过针对每个数据突发调整均衡器系数而引起的误差。 第四种技术通过使用两部分前导码来改善均衡器的收敛，由此两部分都使用不同的调制技术进行发送。 提供了在不执行调制解调器的完全复位的情况下执行调制解调器的软复位的第五种技术。 第六种技术基于输入突发传输的预期调制类型来确定调制解调器适配因子。 第七种技术计算存储的抽头值的相位校正值，并将该值应用于输入信号。
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