Synchronizing clocks across a communication link
    1.
    发明授权
    Synchronizing clocks across a communication link 有权
    通过通信链路同步时钟

    公开(公告)号:US08199779B2

    公开(公告)日:2012-06-12

    申请号:US13021627

    申请日:2011-02-04

    IPC分类号: H04J3/16 G06F15/16 H04B1/38

    摘要: Apparatus, system and method for synchronizing one or more clocks across a communication link. A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave side. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate which is related as n times the slave clock rate. The synchronization signal receipt time indicated by the correlation sample sequence may be refined by interpolating the correlation sample sequence around a best correlation sample to locate a best interpolation at an interpolation resolution smaller than the sample resolution. The best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output. The synchronization signal receipt time thus determined is compared to the expected time based upon the slave clock, which is adjusted until the times match. After initialization, all slave clock errors are preferably accumulated to prevent long-term slip between the slave and master clocks. Formerly independent master and slave clocks synchronized across the communication link constitute a noncommon clock which may be compared on each side of the link to secondary independent clocks, and the secondary independent clocks may then be separately synchronized by adjusting one to have the same difference from its local noncommon clock as the secondary clock on the other side of the link has from its local noncommon clock.

    摘要翻译: 用于在通信链路上同步一个或多个时钟的装置,系统和方法。 从时钟可以通过从主机发送到链路的从时钟侧的同步信号与主时钟同步。 同步信号可以是以从机侧预期的间隔发送的预期信号模式。 从时钟可以将接收的信号与预期同步信号的表示相关,以产生与从时钟速率的n倍相关的第一采样率的相关采样序列。 通过相关采样序列指示的同步信号接收时间可以通过围绕最佳相关样本内插相关采样序列来精细化,以便以小于样本分辨率的插值分辨率定位最佳内插。 可以通过在与最佳内插输出相邻的内插器输出之间进行估计来进一步改进最佳内插。 将这样确定的同步信号接收时间与基于从时钟的预期时间进行比较,该从时钟被调整直到时间匹配。 在初始化之后,优选地累积所有从时钟错误以防止从机和主时钟之间的长期滑动。 通过通信链路同步的以前独立的主,从时钟构成了一个非常见的时钟,可以在链路的每一侧与次级独立时钟进行比较,然后可以通过调整二次独立时钟来与其独立时钟相同的差异 本地非通用时钟作为链路另一侧的辅助时钟源自其本地非通用时钟。

    Synchronizing clocks across a communication link
    2.
    发明授权
    Synchronizing clocks across a communication link 失效
    通过通信链路同步时钟

    公开(公告)号:US07583705B2

    公开(公告)日:2009-09-01

    申请号:US11170391

    申请日:2005-06-29

    IPC分类号: H04J3/06 H04B1/38 H04W4/00

    摘要: One or more clocks are synchronized across a communication link using a synchronization signal sent from a master to a slave clock. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate. The synchronization signal receipt time is compared to the expected time and the slave clock is adjusted until the times match. Master and slave clocks synchronized across the communication link constitute a noncommon clock which may be compared on each side of the link to secondary independent clocks. The secondary independent clocks may be separately synchronized by adjusting one to have the same difference from its local noncommon clock as the secondary clock on the other side of the link has from its local noncommon clock.

    摘要翻译: 使用从主机发送到从时钟的同步信号,通过通信链路同步一个或多个时钟。 同步信号可以是以从站所预期的间隔发送的预期信号模式。 从时钟可以将接收的信号与预期同步信号的表示相关,以产生第一采样率的相关采样序列。 将同步信号接收时间与预期时间进行比较,并调整从时钟直到时间匹配。 通过通信链路同步的主和从时钟构成了一个非常见的时钟,可以在链路的每一侧与次级独立时钟进行比较。 辅助独立时钟可以通过调整一个来独立同步,以使其与本地非常见时钟具有相同的差异,因为链路另一侧的辅助时钟与其本地非常见时钟相同。

    SYNCHRONIZING CLOCKS ACROSS A COMMUNICATION LINK
    3.
    发明申请
    SYNCHRONIZING CLOCKS ACROSS A COMMUNICATION LINK 有权
    通信链路同步时钟

    公开(公告)号:US20110122981A1

    公开(公告)日:2011-05-26

    申请号:US13021627

    申请日:2011-02-04

    IPC分类号: H04L7/00

    摘要: Apparatus, system and method for synchronizing one or more clocks across a communication link. A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave side. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate which is related as n times the slave clock rate. The synchronization signal receipt time indicated by the correlation sample sequence may be refined by interpolating the correlation sample sequence around a best correlation sample to locate a best interpolation at an interpolation resolution smaller than the sample resolution. The best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output. The synchronization signal receipt time thus determined is compared to the expected time based upon the slave clock, which is adjusted until the times match. After initialization, all slave clock errors are preferably accumulated to prevent long-term slip between the slave and master clocks. Formerly independent master and slave clocks synchronized across the communication link constitute a noncommon clock which may be compared on each side of the link to secondary independent clocks, and the secondary independent clocks may then be separately synchronized by adjusting one to have the same difference from its local noncommon clock as the secondary clock on the other side of the link has from its local noncommon clock.

    摘要翻译: 用于在通信链路上同步一个或多个时钟的装置,系统和方法。 从时钟可以通过从主机发送到链路的从时钟侧的同步信号与主时钟同步。 同步信号可以是以从机侧预期的间隔发送的预期信号模式。 从时钟可以将接收的信号与预期同步信号的表示相关,以产生与从时钟速率的n倍相关的第一采样率的相关采样序列。 通过相关采样序列指示的同步信号接收时间可以通过围绕最佳相关样本内插相关采样序列来精细化,以便以小于样本分辨率的插值分辨率定位最佳内插。 可以通过在与最佳内插输出相邻的内插器输出之间进行估计来进一步改进最佳内插。 将这样确定的同步信号接收时间与基于从时钟的预期时间进行比较,该从时钟被调整直到时间匹配。 在初始化之后,优选地累积所有从时钟错误以防止从机和主时钟之间的长期滑动。 通过通信链路同步的以前独立的主,从时钟构成了一个非常见的时钟,可以在链路的每一侧与次级独立时钟进行比较,然后可以通过调整二次独立时钟来与其独立时钟相同的差异 本地非通用时钟作为链路另一侧的辅助时钟源自其本地非通用时钟。

    Synchronizing clocks across a communication link
    4.
    发明授权
    Synchronizing clocks across a communication link 有权
    通过通信链路同步时钟

    公开(公告)号:US07907640B2

    公开(公告)日:2011-03-15

    申请号:US12508431

    申请日:2009-07-23

    IPC分类号: H04J3/16 H04J3/06 H04L7/00

    摘要: A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave side. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate which is related as n times the slave clock rate. A best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output. The synchronization signal receipt time thus determined is compared to the expected time based upon the slave clock, which is adjusted until the times match. The best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output.

    摘要翻译: 从时钟可以通过从主机发送到链路的从时钟侧的同步信号与主时钟同步。 同步信号可以是以从机侧预期的间隔发送的预期信号模式。 从时钟可以将接收的信号与预期同步信号的表示相关,以产生与从时钟速率的n倍相关的第一采样率的相关采样序列。 可以通过在与最佳内插输出相邻的内插器输出之间进行估计来进一步改进最佳内插。 将这样确定的同步信号接收时间与基于从时钟的预期时间进行比较,该从时钟被调整直到时间匹配。 可以通过在与最佳内插输出相邻的内插器输出之间进行估计来进一步改进最佳内插。

    Synchronizing Clocks Across a Communication Link
    5.
    发明申请
    Synchronizing Clocks Across a Communication Link 有权
    通过通信链路同步时钟

    公开(公告)号:US20090279652A1

    公开(公告)日:2009-11-12

    申请号:US12508431

    申请日:2009-07-23

    IPC分类号: H04L7/00

    摘要: Apparatus, system and method for synchronizing one or more clocks across a communication link. A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave side. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate which is related as n times the slave clock rate. The synchronization signal receipt time indicated by the correlation sample sequence may be refined by interpolating the correlation sample sequence around a best correlation sample to locate a best interpolation at an interpolation resolution smaller than the sample resolution. The best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output. The synchronization signal receipt time thus determined is compared to the expected time based upon the slave clock, which is adjusted until the times match. After initialization, all slave clock errors are preferably accumulated to prevent long-term slip between the slave and master clocks. Formerly independent master and slave clocks synchronized across the communication link constitute a noncommon clock which may be compared on each side of the link to secondary independent clocks, and the secondary independent clocks may then be separately synchronized by adjusting one to have the same difference from its local noncommon clock as the secondary clock on the other side of the link has from its local noncommon clock.

    摘要翻译: 用于在通信链路上同步一个或多个时钟的装置,系统和方法。 从时钟可以通过从主机发送到链路的从时钟侧的同步信号与主时钟同步。 同步信号可以是以从机侧预期的间隔发送的预期信号模式。 从时钟可以将接收的信号与预期同步信号的表示相关,以产生与从时钟速率的n倍相关的第一采样率的相关采样序列。 通过相关采样序列指示的同步信号接收时间可以通过围绕最佳相关样本内插相关采样序列来精细化,以便以小于样本分辨率的插值分辨率定位最佳内插。 可以通过在与最佳内插输出相邻的内插器输出之间进行估计来进一步改进最佳内插。 将这样确定的同步信号接收时间与基于从时钟的预期时间进行比较,该从时钟被调整直到时间匹配。 在初始化之后,优选地累积所有从时钟错误以防止从机和主时钟之间的长期滑动。 通过通信链路同步的以前独立的主,从时钟构成了一个非常见的时钟,可以在链路的每一侧与次级独立时钟进行比较,然后可以通过调整二次独立时钟来与其独立时钟相同的差异 本地非通用时钟作为链路另一侧的辅助时钟源自其本地非通用时钟。

    Synchronizing clocks across a communication link
    6.
    发明申请
    Synchronizing clocks across a communication link 失效
    通过通信链路同步时钟

    公开(公告)号:US20070002987A1

    公开(公告)日:2007-01-04

    申请号:US11170391

    申请日:2005-06-29

    IPC分类号: H04L7/00

    摘要: Apparatus, system and method for synchronizing one or more clocks across a communication link. A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave side. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate which is related as n times the slave clock rate. The synchronization signal receipt time indicated by the correlation sample sequence may be refined by interpolating the correlation sample sequence around a best correlation sample to locate a best interpolation at an interpolation resolution smaller than the sample resolution. The best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output. The synchronization signal receipt time thus determined is compared to the expected time based upon the slave clock, which is adjusted until the times match. After initialization, all slave clock errors are preferably accumulated to prevent long-term slip between the slave and master clocks. Formerly independent master and slave clocks synchronized across the communication link constitute a noncommon clock which may be compared on each side of the link to secondary independent clocks, and the secondary independent clocks may then be separately synchronized by adjusting one to have the same difference from its local noncommon clock as the secondary clock on the other side of the link has from its local noncommon clock.

    摘要翻译: 用于在通信链路上同步一个或多个时钟的装置,系统和方法。 从时钟可以通过从主机发送到链路的从时钟侧的同步信号与主时钟同步。 同步信号可以是以从机侧预期的间隔发送的预期信号模式。 从时钟可以将接收的信号与预期同步信号的表示相关,以产生与从时钟速率的n倍相关的第一采样率的相关采样序列。 通过相关采样序列指示的同步信号接收时间可以通过围绕最佳相关样本内插相关采样序列来精细化,以便以小于样本分辨率的插值分辨率定位最佳内插。 可以通过在与最佳内插输出相邻的内插器输出之间进行估计来进一步改进最佳内插。 将这样确定的同步信号接收时间与基于从时钟的预期时间进行比较,该从时钟被调整直到时间匹配。 在初始化之后,优选地累积所有从时钟错误以防止从机和主时钟之间的长期滑动。 通过通信链路同步的以前独立的主,从时钟构成了一个非常见的时钟,可以在链路的每一侧与次级独立时钟进行比较,然后可以通过调整二次独立时钟来与其独立时钟相同的差异 本地非通用时钟作为链路另一侧的辅助时钟源自其本地非通用时钟。

    Equalizer performance enhancements for broadband wireless applications
    9.
    再颁专利
    Equalizer performance enhancements for broadband wireless applications 有权
    宽带无线应用的均衡器性能增强

    公开(公告)号:USRE42021E1

    公开(公告)日:2011-01-04

    申请号:US11187034

    申请日:2005-07-20

    IPC分类号: H04B1/38 H03H7/30 H03K5/159

    摘要: A system and method for enhancing the performance of an equalizer in a modem. Multiple techniques are disclosed which improve the modem performance. A first technique uses stored parameters for each burst from each remote site to demodulate a received data stream. A second technique compensates for the gain droop caused by storing parameters across each burst. A third technique minimizes errors caused by adapting the equalizer coefficients for each data burst by analyzing the SN ratio and error rate of the received burst. A fourth technique improves the convergence of the equalizer by using a two-part preamble, whereby both parts are transmitted using different modulation techniques. A fifth technique is provided which performs a soft reset of the modem without performing a complete reset of the modem. A sixth technique determines a modem adaptation factor based on the expected modulation type of an incoming burst transmission. A seventh technique calculates a phase correction value for the stored tap values and applies the value to the incoming signal.

    摘要翻译: 一种用于增强调制解调器中的均衡器的性能的系统和方法。 公开了改进调制解调器性能的多种技术。 第一种技术使用来自每个远程站点的每个突发的存储参数来解调所接收的数据流。 第二种技术补偿了通过在每个突发之间存储参数而引起的增益下降。 第三种技术通过分析接收到的突发的SN比和错误率来最小化通过针对每个数据突发调整均衡器系数而引起的误差。 第四种技术通过使用两部分前导码来改善均衡器的收敛,由此两部分都使用不同的调制技术进行发送。 提供了在不执行调制解调器的完全复位的情况下执行调制解调器的软复位的第五种技术。 第六种技术基于输入突发传输的预期调制类型来确定调制解调器适配因子。 第七种技术计算存储的抽头值的相位校正值,并将该值应用于输入信号。