公开(公告)号：US06617266B2

公开(公告)日：2003-09-09

申请号：US09834698

申请日：2001-04-12

Applicant: Annabel Susan Nickles ,  Ravi Rajagopalan ,  Pravin Narwankar

Inventor： Annabel Susan Nickles ,  Ravi Rajagopalan ,  Pravin Narwankar

IPC: H01L2131

CPC classification number: C23C16/56 ,  H01L21/3105

Abstract: A process for forming high k dielectric thin films on a substrate, e.g., silicon, by 1) low temperature (500° C. or less) deposition of a dielectric material onto a surface, followed by 2) high temperature post-deposition annealing. The deposition can take place in an oxidative environment, followed by annealing, or alternatively the deposition can take place in a non-oxidative environment (e.g., N2), followed by oxidation and annealing.

Abstract translation: 1）通过1）将电介质材料沉积在表面上，然后2）高温后沉积退火，在衬底（例如硅）上形成高k电介质薄膜的方法，即1）低温（500℃或更低）。 沉积可以在氧化环境中进行，随后退火，或者沉积可以在非氧化环境（例如，N 2）中进行，随后进行氧化和退火。

公开(公告)号：US06548368B1

公开(公告)日：2003-04-15

申请号：US09644941

申请日：2000-08-23

Applicant: Pravin Narwankar ,  Ravi Rajagopalan

Inventor： Pravin Narwankar ,  Ravi Rajagopalan

IPC: H01L2120

CPC classification number: H01L28/40 ,  H01L21/3143 ,  H01L21/3144 ,  H01L21/31604 ,  H01L21/3185

Abstract: Provided is a method of integrating Ta2O5 into an MIS stack capacitor for a semiconductor device by forming a thin SiON layer at the Si/TaO interface using low temperature remote plasma oxidation anneal. Also provided is a method of forming an MIS stack capacitor with improved electrical performance by treating SiO2 with remote plasma nitridation or SiN layer with rapid thermal oxidation or RPO to form a SiON layer prior to Ta2O5 deposition with TAT-DMAE, TAETO or any other Ta-containing precursor.

Abstract translation: 提供了一种通过使用低温远程等离子体氧化退火在Si / TaO界面处形成薄SiON层来将Ta 2 O 5集成到用于半导体器件的MIS堆叠电容器中的方法。 还提供了一种通过用远程等离子体氮化处理SiO 2或具有快速热氧化或RPO的SiN层来形成具有改进的电性能的MIS堆叠电容器的方法，以在与TAT-DMAE，TAETO或任何其它Ta的Ta 2 O 5沉积之前形成SiON层 含有前体。

公开(公告)号：US06677254B2

公开(公告)日：2004-01-13

申请号：US09911947

申请日：2001-07-23

Applicant: Pravin Narwankar ,  Mouloud Bakli ,  Ravi Rajagopalan ,  Randall S. Urdahl ,  Asher Sinensky ,  Shankarram Athreya

Inventor： Pravin Narwankar ,  Mouloud Bakli ,  Ravi Rajagopalan ,  Randall S. Urdahl ,  Asher Sinensky ,  Shankarram Athreya

IPC: H01L2131

CPC classification number: H01L28/40 ,  H01L21/3143 ,  H01L21/31604 ,  H01L28/56

Abstract: The formation of a barrier layer over a high k dielectric layer and deposition of a conducting layer over the barrier layer prevents intermigration between the species of the high k dielectric layer and the conducting layer and prevents oxygen scavenging of the high k dielectric layer. One example of a capacitor stack device provided includes a high k dielectric layer of Ta2O5, a barrier layer of TaON or TiON formed at least in part by a remote plasma process, and a top electrode of TiN. The processes may be conducted at about 300 to 700° C. and are thus useful for low thermal budget applications. Also provided are MIM capacitor constructions and methods in which an insulator layer is formed by remote plasma oxidation of a bottom electrode.

Abstract translation: 在高k电介质层上形成阻挡层并且在阻挡层上沉积导电层可防止高k电介质层与导电层之间的迁移，并防止高k介电层的氧清除。 提供的电容器堆叠装置的一个示例包括Ta 2 O 5的高k电介质层，至少部分由远程等离子体工艺形成的TaON或TiON的阻挡层和TiN的顶部电极。 该方法可以在约300-700℃下进行，因此可用于低热预算应用。 还提供了MIM电容器结构和其中通过底部电极的远程等离子体氧化形成绝缘体层的方法。

公开(公告)号：US20120279123A1

公开(公告)日：2012-11-08

申请号：US13101226

申请日：2011-05-05

Applicant: Ravi Rajagopalan

Inventor： Ravi Rajagopalan

IPC: A01G9/02 ,  B65D1/40

CPC classification number: A01G9/021

Abstract: An injection molded container such as a flower pot having an outer surface and an inner surface and an indentation of a shape and size corresponding to the shape and size of a design element member, the design element member and the container member adapted to easily engage one another and to be easily disengaged so as to provide at least one decorative element on the outside surface of the container which can be easily changed according to a selectable design scheme.

Abstract translation: 一种注塑容器，例如具有外表面和内表面的花盆，以及与设计元件构件的形状和尺寸相对应的形状和尺寸的凹陷，设计元件构件和容器构件适于容易地接合一个 另一个并且易于脱开，以便在容器的外表面上提供至少一个装饰元件，其可以根据可选择的设计方案容易地改变。

公开(公告)号：US06204174B1

公开(公告)日：2001-03-20

申请号：US08977831

申请日：1997-11-25

Applicant: Alexander D. Glew ,  Andrew D. Johnson ,  Ravi Rajagopalan ,  Steve Ghanayem

Inventor： Alexander D. Glew ,  Andrew D. Johnson ,  Ravi Rajagopalan ,  Steve Ghanayem

IPC: H01L2144

CPC classification number: H01L21/28568 ,  C23C16/14 ,  C23C16/52 ,  H01L21/76877

Abstract: A method and apparatus to control the deposition rate of a refractory metal film in a semiconductor fabrication process by controlling a quantity of ethylene present. The method includes placing a substrate in a deposition zone, of a semiconductor process chamber, flowing, into the deposition zone, a process gas including a refractory metal source, an inert carrier gas, and a hydrocarbon. Typically, the refractory metal source is tungsten hexafluoride, WF6, and the inert gas is argon, Ar. The ethylene may be premixed with either the argon or the tungsten hexafluoride to form a homogenous mixture. However, an in situ mixing apparatus may also be employed.

Abstract translation: 通过控制存在的乙烯量来控制半导体制造工艺中难熔金属膜的沉积速率的方法和装置。 该方法包括将衬底放置在半导体处理室的沉积区中，流入沉积区，包括难熔金属源，惰性载气和烃的工艺气体。 通常，难熔金属源是六氟化钨，WF 6，惰性气体是氩，Ar。 乙烯可以与氩气或六氟化钨预混合以形成均匀的混合物。 然而，也可以使用原位混合装置。

公开(公告)号：US08499208B2

公开(公告)日：2013-07-30

申请号：US11553609

申请日：2006-10-27

Applicant: James Norris Dieffenderfer ,  Anand Krishnamurthy ,  Clint Wayne Mumford ,  Jason Lawrence Panavich ,  Ketan Vitthal Patel ,  Ravi Rajagopalan ,  Thomas Philip Speier

Inventor： James Norris Dieffenderfer ,  Anand Krishnamurthy ,  Clint Wayne Mumford ,  Jason Lawrence Panavich ,  Ketan Vitthal Patel ,  Ravi Rajagopalan ,  Thomas Philip Speier

IPC: G01R31/28

CPC classification number: G01R31/31707 ,  G01R31/3187

Abstract: The content and order of a predetermined sequence of hard-coded and/or quasi-programmable test patterns may be altered during a Built-In Self-Test (BIST) routine. As such, knowledge gained post design completion may be reflected in the selection and arrangement of available tests to be executed during a BIST routine. In one embodiment, a sequence of hard-coded and/or quasi-programmable tests is executed during a BIST routine by receiving test ordering information for the sequence of tests and executing the sequence of tests in an order indicated by the test ordering information. A corresponding BIST circuit comprises a storage element and a state machine. The storage element is configured to store test ordering information for the sequence of tests. The state machine is configured to execute the sequence of tests in an order indicated by the test ordering information.

Abstract translation: 硬编码和/或准可编程测试图案的预定顺序的内容和顺序可以在内置自检（BIST）程序期间改变。 因此，获得后期设计完成的知识可能反映在BIST程序中执行的可用测试的选择和排列。 在一个实施例中，在BIST程序期间，通过接收测试序列的测试排序信息并按测试顺序信息指示的顺序执行测试序列来执行硬编码和/或准可编程测试序列。 相应的BIST电路包括存储元件和状态机。 存储元件被配置为存储测试序列的测试排序信息。 状态机被配置为按照测试顺序信息所示的顺序执行测试序列。

公开(公告)号：US08443162B2

公开(公告)日：2013-05-14

申请号：US11040600

申请日：2005-01-21

Applicant: Thomas Philip Speier ,  James Norris Dieffenderfer ,  Ravi Rajagopalan

Inventor： Thomas Philip Speier ,  James Norris Dieffenderfer ,  Ravi Rajagopalan

IPC: G06F13/00 ,  G06F13/28

CPC classification number: G06F12/0802 ,  G06F12/0851 ,  G06F2212/601 ,  Y02D10/13

Abstract: Techniques for controllably allocating a portion of a plurality of memory banks as cache memory are disclosed. To this end, a configuration tracker and a bank selector are employed. The configuration tracker configures whether each memory bank is to operate in a cache or not. The bank selector has a plurality of bank distributing functions. Upon receiving an incoming address, the bank selector determines the configuration of memory banks currently operating as the cache and applies an appropriate bank distributing function based on the configuration of memory banks. The applied bank distributing function utilizes bits in the incoming address to access one of the banks configured as being in the cache.

Abstract translation: 公开了用于可控地分配多个存储体的一部分作为高速缓冲存储器的技术。 为此，采用配置跟踪器和存储体选择器。 配置跟踪器配置每个存储器是否要在高速缓存中运行。 银行选择器具有多个银行分配功能。 在接收到输入地址时，存储体选择器确定当前作为缓存操作的存储器组的配置，并且基于存储体的配置应用适当的存储体分配功能。 应用的银行分配功能利用输入地址中的位来访问配置为处于高速缓存中的银行之一。

公开(公告)号：US06070599A

公开(公告)日：2000-06-06

申请号：US942582

申请日：1997-10-02

Applicant: Steve Ghanayem ,  Moris Kori ,  Maitreyee Mahajani ,  Ravi Rajagopalan

Inventor： Steve Ghanayem ,  Moris Kori ,  Maitreyee Mahajani ,  Ravi Rajagopalan

IPC: C23C16/02 ,  C23C16/44 ,  C23C16/455 ,  C23C16/52 ,  H01L21/302 ,  H01L21/3065 ,  B08B3/12

CPC classification number: C23C16/52 ,  C23C16/02 ,  C23C16/4405

Abstract: An apparatus and process for limiting residue remaining after the etching of metal in a semiconductor manufacturing process, such as etching back a tungsten layer to form tungsten plugs, by passivating the surface of a wafer with a halogen-containing gas are disclosed. The wafer is exposed to the halogen-containing gas in a chamber before a metal layer is deposited on the wafer. The exposure can occur in the same chamber as the metal deposition, or a different chamber. The wafer can remain in the chamber or be moved to another chamber for etching after exposure and deposition.

Abstract translation: 公开了一种用于限制在半导体制造工艺中蚀刻金属后残留的残留物的设备和方法，例如通过用含卤素气体钝化晶片的表面来蚀刻钨层以形成钨插塞。 在将金属层沉积在晶片上之前，将晶片暴露于腔室中的含卤素气体。 曝光可能发生在与金属沉积相同的室中，或者在不同的室中。 晶片可以保留在腔室中，或者在曝光和沉积之后移动到另一个腔室进行蚀刻。

公开(公告)号：US20150013223A1

公开(公告)日：2015-01-15

申请号：US14328980

申请日：2014-07-11

Applicant: Ravi Rajagopalan

Inventor： Ravi Rajagopalan

IPC: A01G9/02

CPC classification number: A01G9/025 ,  Y02P60/244

Abstract: A vertical planter having a partitioned tray, a liner, and a sliding wire support grid, wherein the partitioned tray engages the sliding wire support grid to provide access to the partitioned tray.

Abstract translation: 具有分隔盘，衬套和滑动线支撑栅格的垂直播种机，其中所述分隔盘与滑动线支撑栅格啮合以提供对分隔盘的通路。

公开(公告)号：US07621075B2

公开(公告)日：2009-11-24

申请号：US10903979

申请日：2004-07-30

Applicant: Ravi Rajagopalan

Inventor： Ravi Rajagopalan

IPC: A01G9/02

CPC classification number: A01G9/024

Abstract: A liner for use in a horticultural planter contains an integral water tray which is located between inner and outer fibrous layers of a liner. The water tray extends from a bottom surface of the liner toward a peripheral top edge. An overflow region is included with the water tray near the peripheral top edge of the liner.

Abstract translation: 用于园艺种植机的衬里包含位于衬里的内纤维层和外纤维层之间的整体水盘。 水盘从衬垫的底表面朝向周边顶部边缘延伸。 在靠近衬管的周边顶部边缘的水盘中包括溢流区域。