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公开(公告)号：US06421389B1
公开(公告)日：2002-07-16
申请号：US09356384
申请日：1999-07-16
IPC分类号： H04L2700
CPC分类号： H04L25/4902 , H04B1/71637 , H04B1/7183 , H04B1/719
摘要： A baseband signal converter device for an impulse radio receiver combines multiple converter circuits and an RF amplifier in a single integrated circuit package. Each converter circuit includes an integrator circuit that integrates a portion of each RF pulse during a sampling period triggered by a timing pulse generator. The integrator capacitor is isolated by a pair of Schottky diodes connected to a pair of load resistors. A current equalizer circuit equalizes the current flowing through the load resistors when the integrator is not sampling. Current steering logic transfers load current between the diodes and a constant bias circuit depending on whether a sampling pulse is present.
摘要翻译： 用于脉冲无线电接收机的基带信号转换器装置将多个转换器电路和RF放大器组合在单个集成电路封装中。 每个转换器电路包括积分器电路，其在由定时脉冲发生器触发的采样周期期间对每个RF脉冲的一部分进行积分。 积分器电容由一对连接到一对负载电阻的肖特基二极管隔离。 当积分器不采样时，电流均衡器电路均衡流过负载电阻器的电流。 电流转向逻辑根据是否存在采样脉冲，传输二极管之间的负载电流和恒定偏置电路。
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公开(公告)号：US06937663B2
公开(公告)日：2005-08-30
申请号：US10055007
申请日：2002-01-23
IPC分类号： H04B1/7163 , H04B1/7183 , H04B1/719 , H04L25/49 , H04L27/00
CPC分类号： H04L25/4902 , H04B1/71637 , H04B1/7183 , H04B1/719
摘要： A baseband signal converter device for an impulse radio receiver combines multiple converter circuits and an RF amplifier in a single integrated circuit package. Each converter circuit includes an integrator circuit that integrates a portion of each RF pulse during a sampling period triggered by a timing pulse generator. The integrator capacitor is isolated by a pair of Schottky diodes connected to a pair of load resistors. A current equalizer circuit equalizes the current flowing through the load resistors when the integrator is not sampling. Current steering logic transfers load current between the diodes and a constant bias circuit depending on whether a sampling pulse is present.
摘要翻译： 用于脉冲无线电接收机的基带信号转换器装置将多个转换器电路和RF放大器组合在单个集成电路封装中。 每个转换器电路包括积分器电路，其在由定时脉冲发生器触发的采样周期期间对每个RF脉冲的一部分进行积分。 积分器电容由一对连接到一对负载电阻的肖特基二极管隔离。 当积分器不采样时，电流均衡器电路均衡流过负载电阻器的电流。 电流转向逻辑根据是否存在采样脉冲，传输二极管之间的负载电流和恒定偏置电路。
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公开(公告)号：US06304623B1
公开(公告)日：2001-10-16
申请号：US09146524
申请日：1998-09-03
IPC分类号： H04C700
CPC分类号： H03L7/18 , H04B1/7163 , H04B1/71635 , H04B1/7183
摘要： A frame reference signal is produced as a function of a clock signal. A first timing generator generates a coarse timing signal having a nominal period and a transition occurring at a precise temporal position with respect to the nominal period. The nominal period is a function of the frame reference signal. The temporal position is a function of a first input timing command and the clock signal. A second timing generator generates at least one fine timing transition as a function of a second input timing command and the clock signal. A combiner circuit uses the coarse timing signal to select one of the at least one fine timing transitions to output a precise timing signal, wherein the precise timing signal has a high temporal precision with respect to the frame reference signal.
摘要翻译： 作为时钟信号的函数产生帧参考信号。 第一定时发生器产生具有标称周期和在相对于标称周期的精确时间位置发生的转变的粗定时信号。 标称周期是帧参考信号的函数。 时间位置是第一输入定时命令和时钟信号的函数。 第二定时发生器产生作为第二输入定时命令和时钟信号的函数的至少一个精细定时转换。 组合器电路使用粗定时信号来选择至少一个精细定时转换中的一个以输出精确定时信号，其中精确定时信号相对于帧参考信号具有高的时间精度。
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公开(公告)号：US06950485B2
公开(公告)日：2005-09-27
申请号：US10329739
申请日：2002-12-26
IPC分类号： H03L7/00 , G01S7/282 , G01S13/02 , G01S13/10 , H03D3/24 , H03K5/135 , H03L7/18 , H04B20060101 , H04B1/69 , H04B14/02 , H04J3/06 , H04L1/08 , H04L7/00 , H04L7/08 , H04L25/40
CPC分类号： H04B1/7183 , G01S7/282 , G01S13/0209 , G01S13/106 , H03L7/18 , H04B1/71635 , H04L1/08
摘要： A precision timing generator includes a combiner that provides a timing signal by combining a coarse timing signal and a fine timing signal derived from a phase-shifted sinusoidal signal that has a desired phase shift. The coarse timing generator generates the coarse timing signal from a clock signal and a timing command input. The fine timing generator includes a sinusoidal-signal generator that receives the clock signal and generates a sinusoidal signal. The fine timing generator also includes a phase shifter that receives the sinusoidal signal and the timing command input and shifts the phase of the sinusoidal signal based on the timing input to generate the phase shifted sinusoidal signal.
摘要翻译： 精确定时发生器包括组合器，其通过组合粗定时信号和从具有期望相移的相移正弦信号导出的精细定时信号来提供定时信号。 粗定时发生器从时钟信号和定时命令输入产生粗定时信号。 精确定时发生器包括正弦信号发生器，其接收时钟信号并产生正弦信号。 精确定时发生器还包括接收正弦信号和定时指令输入的移相器，并且基于定时输入偏移正弦信号的相位，以产生相移的正弦信号。
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公开(公告)号：US06577691B2
公开(公告)日：2003-06-10
申请号：US09910178
申请日：2001-07-20
IPC分类号： H04L700
CPC分类号： H04B1/7183 , G01S7/282 , G01S13/0209 , G01S13/106 , H03L7/18 , H04B1/71635 , H04L1/08
摘要： A precision timing generator includes a combiner that provides a timing signal by combining a coarse timing signal and a fine timing signal derived from a phase-shifted sinusoidal signal that has a desired phase shift. The coarse timing generator generates the coarse timing signal from a clock signal and a timing command input. The fine timing generator includes a sinusoidal-signal generator that receives the clock signal and generates a sinusoidal signal. The fine timing generator also includes a phase shifter that receives the sinusoidal signal and the timing command input and shifts the phase of the sinusoidal signal based on the timing input to generate the phase shifted sinusoidal signal.
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6.发明授权Microwave/millimeter wave circuit structure with discrete flip-chip mounted elements 失效微波/毫米波电路结构，具有分立的倒装芯片安装元件
公开(公告)号：US5757074A
公开(公告)日：1998-05-26
申请号：US681688
申请日：1996-07-29
CPC分类号： H01L25/162 , H01L23/66 , H01L24/81 , H01Q23/00 , H05K3/3452 , H01L2223/6677 , H01L2224/13111 , H01L2224/16 , H01L2224/81801 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01068 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/1305 , H01L2924/13064 , H01L2924/14 , H01L2924/1423 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H05K1/0237 , H05K2201/0175 , H05K2203/0315
摘要： A microwave/millimeter wave circuit structure supports discrete circuit elements by flip-chip mounting to an interconnection network on a low cost non-ceramic and non-semiconductor dielectric substrate, preferably Duroid. The necessary precise alignment of the circuit elements with contact pads on the substrate network required for the high operating frequencies is facilitated by oxidizing the interconnection network, but providing the contact pads from a non-oxidizable material to establish a preferential solder bump wetting for the pads. Alternately, the contact bumps on the flip-chips can be precisely positioned through corresponding openings in a passivation layer over the interconnection network. For thin circuit substrates that are too soft for successful flip-chip mounting, stiffening substrates are laminated to the circuit substrates. In a self-contained antenna application in which two of the circuit substrates are laminated together, with an antenna on one side and circuitry on the other side, a metallic ground plane between the substrates also serves a stiffening function.
摘要翻译： 微波/毫米波电路结构通过倒装芯片安装到低成本非陶瓷和非半导体电介质基底（优选为Duroid）上的互连网络来支持分立电路元件。 通过氧化互连网络来提供电路元件与高工作频率所需的基板网络上的接触焊盘的必要精确对准，但是提供来自不可氧化材料的接触焊盘以建立用于焊盘的优先焊料凸块润湿 。 或者，倒装芯片上的接触凸块可以通过互连网络上的钝化层中的相应开口精确定位。 对于对于成功倒装芯片安装来说太软的薄电路基板，加固基板被层压到电路基板上。 在其中两个电路基板层叠在一起的独立天线应用中，一侧的天线和另一侧的电路，在基板之间的金属接地平面也起增强作用。
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7.发明授权Immediate duplication of I/O requests on a record by record basis by a computer operating system 失效通过计算机操作系统在记录基础上立即重复I / O请求
公开(公告)号：US5072368A
公开(公告)日：1991-12-10
申请号：US571836
申请日：1990-08-24
摘要： A method for ensuring data integrity in a computer system having a primary logical device and one or more alternate logical devices. These logical devices have substantially identical data stored in them and have the capability of responding to requests. The system duplicates device access to the alternate logical devices. The logical devices are identified to the computer system as the devices on which duplicating or mirroring operations are to be performed. A read operation or a write operation is performed on the primary logical device. In the case of a write operation, it is also performed simultaneously on the alternate logical devices. The system waits for a response from the primary logical device. If the response indicates that the primary logical device has failed, the alternate logical devices are relied on to complete the operation.
摘要翻译： 一种用于确保具有主逻辑设备和一个或多个备用逻辑设备的计算机系统中的数据完整性的方法。 这些逻辑设备具有存储在其中的基本相同的数据，并具有响应请求的能力。 该系统复制对备用逻辑设备的设备访问。 将逻辑设备识别为计算机系统作为要执行复制或镜像操作的设备。 在主逻辑设备上执行读操作或写操作。 在写操作的情况下，它也在备用逻辑设备上同时执行。 系统等待主逻辑设备的响应。 如果响应指示主逻辑设备发生故障，则依赖备用逻辑设备完成操作。
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公开(公告)号：US4951303A
公开(公告)日：1990-08-21
申请号：US264935
申请日：1988-10-31
申请人： Lawrence E. Larson
发明人： Lawrence E. Larson
CPC分类号： H03K23/44 , H03K23/544 , H03K23/667
摘要： A high speed digital programmable frequency divider (100) capable of frequency division by even and odd integers is disclosed herein. The frequency divider (100) of the present invention includes a waveform generator (200) for providing a periodic input waveform of a first period and the inverse thereof. The present invention further includes a clocked ring oscillator circuit (400) for providing first and second closed signal paths, in response to the input waveform, disposed to invert signals passing therethrough. The first and second signal paths have a common output node (499) and first and second propagation delays substantially equal to first and second integral multiples of the first period, respectively. In addition, the frequency divider (100) includes a programmable switch network (500) for opening the first and second signal paths to provide a periodic output waveform at the output node (499).
摘要翻译： 本文公开了能够通过偶数和奇数整数分频的高速数字可编程分频器（100）。 本发明的分频器（100）包括用于提供第一周期的周期性输入波形及其反相的波形发生器（200）。 本发明还包括时钟环形振荡器电路（400），用于响应输入波形提供第一和第二闭合信号路径，该输入波形被设置为反转通过其中的信号。 第一和第二信号路径分别具有公共输出节点（499）和基本上等于第一周期的第一和第二整数倍的第一和第二传播延迟。 此外，分频器（100）包括用于打开第一和第二信号路径以在输出节点（499）提供周期性输出波形的可编程开关网络（500）。
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公开(公告)号：US07652532B2
公开(公告)日：2010-01-26
申请号：US11515584
申请日：2006-09-05
申请人： Mingyuan Li , Peter Asbeck , Ian Galton , Lawrence E. Larson
发明人： Mingyuan Li , Peter Asbeck , Ian Galton , Lawrence E. Larson
IPC分类号： H03F1/32
CPC分类号： H03F1/3247 , G01R31/2822 , G01R31/2839 , H03F1/3258
摘要： The invention provides methods and devices for estimating power amplifier nonlinearity using simple correlation techniques. Methods and devices of the invention can monitor a power amplifier that has digitally modulated inputs and an output containing more than one signal stream. A preferred method of the invention creates a test signal by forming the products of several pseudorandom noise sequences from the digitally modulated inputs to the power amplifier. Nonlinear contributions of the power amplifier output are determined by cross-correlating the test signal and the total output signal of the power amplifier. In preferred embodiments, the determined nonlinear contributions of the power amplifier are used to introduce corrective predistortion in the power amplifier.
摘要翻译： 本发明提供了使用简单相关技术来估计功率放大器非线性的方法和装置。 本发明的方法和装置可以监视具有数字调制输入的功率放大器和包含多于一个信号流的输出。 本发明的优选方法通过形成从数字调制输入到功率放大器的几个伪随机噪声序列的乘积来产生测试信号。 功率放大器输出的非线性贡献由功率放大器的测试信号和总输出信号的互相关来确定。 在优选实施例中，功率放大器的确定的非线性贡献用于在功率放大器中引入校正预失真。
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10.发明申请公开(公告)号：US20090134960A1
公开(公告)日：2009-05-28
申请号：US11920935
申请日：2006-06-06
IPC分类号： H03J3/20
CPC分类号： H01L29/93 , H01L27/0811
摘要： An integrated variable voltage diode capacitor topology applied to a circuit providing a variable voltage load for controlling variable capacitance. The topology includes a first pair of anti-series varactor diodes, wherein the diode power-law exponent n for the first pair of anti-series varactor diodes in the circuit is equal or greater than 0.5, and the first pair of anti-series varactor diodes have an unequal size ratio that is set to control third-order distortion. The topology also includes a center tap between the first pair anti-series varactor diodes for application of the variable voltage load. In preferred embodiments, a second pair of anti-series varactor diodes is arranged anti-parallel to the first pair of anti-series varactor diodes so the combination of the first pair of anti-series varactor diodes and the second pair of anti-series varactor diodes control second-order distortion as well.
摘要翻译： 集成的可变电压二极管电容器拓扑应用于提供用于控制可变电容的可变电压负载的电路。 拓扑结构包括第一对抗串联变容二极管，其中电路中第一对抗串联变容二极管的二极管幂律指数n等于或大于0.5，第一对抗串联变容二极管 二极管具有不等的尺寸比，其被设置为控制三阶失真。 拓扑结构还包括用于施加可变电压负载的第一对抗串联变容二极管之间的中心抽头。 在优选实施例中，第二对抗串联变容二极管被布置成与第一对抗串联变容二极管反平行，因此第一对抗串联变容二极管和第二对抗串联变容二极管的组合 二极管也控制二阶失真。
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