公开(公告)号：US08963611B2

公开(公告)日：2015-02-24

申请号：US12580988

申请日：2009-10-16

申请人： Puay Hoe See ,  Gary J. Ballantyne ,  Gurkanwal Singh Sahota ,  Aristotele Hadjichristos ,  Alberto Cicalini

发明人： Puay Hoe See ,  Gary J. Ballantyne ,  Gurkanwal Singh Sahota ,  Aristotele Hadjichristos ,  Alberto Cicalini

IPC分类号： G06G7/16

CPC分类号： H04B1/0458 ,  H03H7/40

摘要： Exemplary embodiments disclosed are directed to power and impedance measurement circuits that may be used to measure power and/or impedance are described. A measurement circuit may include a sensor and a computation unit. The sensor may sense (i) a first voltage signal across a series circuit coupled to a load to obtain a first sensed signal and (ii) a second voltage signal at a designated end of the series circuit to obtain a second sensed signal. The sensor may mix (i) a first version of the first sensed signal with a first version of the second sensed signal to obtain a first sensor output and (ii) a second version of the first sensed signal with a second version of the second sensed signal to obtain a second sensor output. The computation unit may determine the impedance and/or delivered power at the designated end of the series circuit based on the sensor outputs.

摘要翻译： 所公开的示例性实施例涉及可用于测量功率和/或阻抗的功率和阻抗测量电路。 测量电路可以包括传感器和计算单元。 传感器可以感测（i）跨耦合到负载的串联电路的第一电压信号以获得第一感测信号，以及（ii）串联电路的指定端的第二电压信号以获得第二感测信号。 传感器可以将（i）第一感测信号的第一版本与第二感测信号的第一版本混合以获得第一传感器输出，以及（ii）第一感测信号的第二版本，具有第二感测的第二版本 信号以获得第二传感器输出。 计算单元可以基于传感器输出来确定串联电路的指定端处的阻抗和/或传递功率。

公开(公告)号：US20100321086A1

公开(公告)日：2010-12-23

申请号：US12580988

申请日：2009-10-16

申请人： Puay Hoe See ,  Gary J. Ballantyne ,  Gurkanwal Singh Sahota ,  Aristotele Hadjichristos ,  Alberto Cicalini

发明人： Puay Hoe See ,  Gary J. Ballantyne ,  Gurkanwal Singh Sahota ,  Aristotele Hadjichristos ,  Alberto Cicalini

IPC分类号： G06F7/44

CPC分类号： H04B1/0458 ,  H03H7/40

摘要： Exemplary embodiments disclosed are directed to power and impedance measurement circuits that may be used to measure power and/or impedance are described. A measurement circuit may include a sensor and a computation unit. The sensor may sense (i) a first voltage signal across a series circuit coupled to a load to obtain a first sensed signal and (ii) a second voltage signal at a designated end of the series circuit to obtain a second sensed signal. The sensor may mix (i) a first version of the first sensed signal with a first version of the second sensed signal to obtain a first sensor output and (ii) a second version of the first sensed signal with a second version of the second sensed signal to obtain a second sensor output. The computation unit may determine the impedance and/or delivered power at the designated end of the series circuit based on the sensor outputs.

摘要翻译： 所公开的示例性实施例涉及可用于测量功率和/或阻抗的功率和阻抗测量电路。 测量电路可以包括传感器和计算单元。 传感器可以感测（i）跨耦合到负载的串联电路的第一电压信号以获得第一感测信号，以及（ii）串联电路的指定端的第二电压信号以获得第二感测信号。 传感器可以将（i）第一感测信号的第一版本与第二感测信号的第一版本混合以获得第一传感器输出，以及（ii）第一感测信号的第二版本，具有第二感测的第二版本 信号以获得第二传感器输出。 计算单元可以基于传感器输出来确定串联电路的指定端处的阻抗和/或传递功率。

公开(公告)号：US08072255B2

公开(公告)日：2011-12-06

申请号：US11970311

申请日：2008-01-07

申请人： Alberto Cicalini

发明人： Alberto Cicalini

IPC分类号： G06G7/12

CPC分类号： H03D7/1441 ,  H03D7/145 ,  H03D7/1458 ,  H03D7/165 ,  H03D2200/0084

摘要： In one embodiment of the invention, a method for convolution of signals is disclosed including generating four phased half duty cycle clocks each being out of phase by a multiple of ninety degrees from the others; coupling the four phased half duty cycle clocks into a four phase half duty cycle mixer; and switching switches in the four phase half duty cycle mixer in response to the four phased half duty cycle clocks to convolve a differential input signal with the four phased half duty cycle clocks to concurrently generate a differential in-phase output signal and a differential quadrature-phase output signal on a dual differential output port.

摘要翻译： 在本发明的一个实施例中，公开了一种用于卷积信号的方法，包括产生四个相位半占空比时钟，每个相位与其他时钟相位相差九十度; 将四个相位半占空比时钟耦合到四相半占空比混频器中; 以及四相半占空比混频器中的开关开关，以响应于四个相位半占空比时钟，以将差分输入信号与四个相位半占空比时钟进行并入，以同时产生差分同相输出信号和差分正交输出信号， 双差分输出端口的相位输出信号。

公开(公告)号：US20100103571A1

公开(公告)日：2010-04-29

申请号：US12259158

申请日：2008-10-27

申请人： Gary Lee Brown, JR. ,  Alberto Cicalini

发明人： Gary Lee Brown, JR. ,  Alberto Cicalini

IPC分类号： H02H9/04

CPC分类号： H03K17/08104 ,  H01L27/0248 ,  H03F2200/294 ,  H03F2200/451

摘要： During an ESD event, an ESD current flows from a ground node of a first ESD protection circuit and out of an integrated circuit to a terminal of a package that houses the integrated circuit. To improve ESD performance, a second ESD protection circuit is provided. A diode of the second ESD protection circuit is coupled between the ground node and the body of an input transistor of a Low Noise Amplifier (LNA). If the voltage on the ground node changes quickly during an ESD event (for example, due to a current spike flowing across a wire bond), then the diode charges the body of the transistor, thereby preventing a large gate-to-body voltage from developing across transistor. In some embodiments, another ground bond pad is provided and the second ESD protection circuit includes other diodes that charge or discharge other nodes during the ESD event to prevent transistor damage.

摘要翻译： 在ESD事件期间，ESD电流从第一ESD保护电路的接地节点流出集成电路到容纳集成电路的封装的端子。 为了提高ESD性能，提供了第二个ESD保护电路。 第二ESD保护电路的二极管耦合在接地节点和低噪声放大器（LNA）的输入晶体管的主体之间。 如果在ESD事件期间接地节点上的电压变化很快（例如，由于电流尖峰流过引线键合），则二极管会对晶体管的体进行充电，从而防止大的门对电压 跨晶体管开发。 在一些实施例中，提供另一接地焊盘，并且第二ESD保护电路包括在ESD事件期间对其他节点进行充电或放电以防止晶体管损坏的其它二极管。

公开(公告)号：US20120049928A1

公开(公告)日：2012-03-01

申请号：US13289249

申请日：2011-11-04

申请人： Alberto Cicalini

发明人： Alberto Cicalini

IPC分类号： G06G7/12

CPC分类号： H03D7/1441 ,  H03D7/145 ,  H03D7/1458 ,  H03D7/165 ,  H03D2200/0084

摘要： In one embodiment of the invention, a method for convolution of signals is disclosed including generating four phased half duty cycle clocks each being out of phase by a multiple of ninety degrees from the others; coupling the four phased half duty cycle clocks into a four phase half duty cycle mixer; and switching switches in the four phase half duty cycle mixer in response to the four phased half duty cycle clocks to convolve a differential input signal with the four phased half duty cycle clocks to concurrently generate a differential in-phase output signal and a differential quadrature-phase output signal on a dual differential output port.

摘要翻译： 在本发明的一个实施例中，公开了一种用于卷积信号的方法，包括产生四个相位半占空比时钟，每个相位与其他时钟相位相差九十度; 将四个相位半占空比时钟耦合到四相半占空比混频器中; 以及四相半占空比混频器中的开关开关，以响应于四个相位半占空比时钟，以将差分输入信号与四个相位半占空比时钟进行并入，以同时产生差分同相输出信号和差分正交输出信号， 双差分输出端口的相位输出信号。

公开(公告)号：US20070236202A1

公开(公告)日：2007-10-11

申请号：US11400592

申请日：2006-04-07

申请人： Alberto Cicalini

发明人： Alberto Cicalini

IPC分类号： G05F3/16

CPC分类号： G05F3/205

摘要： A bias generator comprises a first transistor and a second transistor having a control port connected to a control port of the first transistor and to an input port of the second transistor, where a second current through the second transistor is greater than a first current through the first transistor. The current through the bias generator is minimized by providing the different currents through the transistors having a similar size.

摘要翻译： 偏置发生器包括第一晶体管和第二晶体管，其具有连接到第一晶体管的控制端口和第二晶体管的输入端口的控制端口，其中通过第二晶体管的第二电流大于通过第二晶体管的第一电流 第一晶体管。 通过提供通过具有相似尺寸的晶体管的不同电流来最小化通过偏置发生器的电流。

公开(公告)号：US08525573B2

公开(公告)日：2013-09-03

申请号：US13289249

申请日：2011-11-04

申请人： Alberto Cicalini

发明人： Alberto Cicalini

IPC分类号： G06G7/12

CPC分类号： H03D7/1441 ,  H03D7/145 ,  H03D7/1458 ,  H03D7/165 ,  H03D2200/0084

摘要： In one embodiment of the invention, a method for convolution of signals is disclosed including generating four phased half duty cycle clocks each being out of phase by a multiple of ninety degrees from the others; coupling the four phased half duty cycle clocks into a four phase half duty cycle mixer; and switching switches in the four phase half duty cycle mixer in response to the four phased half duty cycle clocks to convolve a differential input signal with the four phased half duty cycle clocks to concurrently generate a differential in-phase output signal and a differential quadrature-phase output signal on a dual differential output port.

摘要翻译： 在本发明的一个实施例中，公开了一种用于卷积信号的方法，包括产生四个相位半占空比时钟，每个相位与其他时钟相位相差九十度; 将四个相位半占空比时钟耦合到四相半占空比混频器中; 以及四相半占空比混频器中的开关开关，以响应于四个相位半占空比时钟，以将差分输入信号与四个相位半占空比时钟进行并入，以同时产生差分同相输出信号和差分正交输出信号， 双差分输出端口的相位输出信号。

公开(公告)号：US07646236B2

公开(公告)日：2010-01-12

申请号：US11399987

申请日：2006-04-07

申请人： Alberto Cicalini

发明人： Alberto Cicalini

IPC分类号： H04B1/10

CPC分类号： H03H1/02 ,  H03H2210/021 ,  H03H2210/043

摘要： A two-step tuning process for resistors and capacitors in an integrated circuit is described. In the first step of the tuning process, an on-chip adjustable resistor is tuned based on an external resistor to obtain a tuned resistor. The value of the tuned resistor is accurate to within a target percentage determined by the external resistor and the design of the adjustable resistor. In the second step, an adjustable capacitor is tuned based on the tuned resistor and an accurate clock to obtain a tuned capacitor having an accurate value. The adjustable capacitor may be tuned such that an RC time constant for the tuned resistor and the tune capacitor is accurate to within a target percentage determined by the accurate clock and the design of the adjustable capacitor. The resistors and capacitors of other circuits on the integrated circuit may be adjusted based on the tuned resistor and the tuned capacitor, respectively.

摘要翻译： 描述了集成电路中的电阻器和电容器的两步调谐过程。 在调谐过程的第一步中，基于外部电阻器调整片上可调电阻以获得调谐电阻。 调谐电阻的值精确到由外部电阻确定的目标百分比和可调电阻的设计之内。 在第二步中，基于调谐电阻器和精确时钟来调节可调电容器以获得具有准确值的调谐电容器。 可调整的可调电容器可以使得调谐电阻器和调谐电容器的RC时间常数精确到由精确时钟和可调电容器的设计确定的目标百分比之内。 可以分别基于调谐电阻器和调谐电容器来调整集成电路上的其它电路的电阻器和电容器。

公开(公告)号：US20090174459A1

公开(公告)日：2009-07-09

申请号：US11970311

申请日：2008-01-07

申请人： Alberto Cicalini

发明人： Alberto Cicalini

IPC分类号： H03H11/22

CPC分类号： H03D7/1441 ,  H03D7/145 ,  H03D7/1458 ,  H03D7/165 ,  H03D2200/0084

摘要： In one embodiment of the invention, a method for convolution of signals is disclosed including generating four phased half duty cycle clocks each being out of phase by a multiple of ninety degrees from the others; coupling the four phased half duty cycle clocks into a four phase half duty cycle mixer; and switching switches in the four phase half duty cycle mixer in response to the four phased half duty cycle clocks to convolve a differential input signal with the four phased half duty cycle clocks to concurrently generate a differential in-phase output signal and a differential quadrature-phase output signal on a dual differential output port.

摘要翻译： 在本发明的一个实施例中，公开了一种用于卷积信号的方法，包括产生四个相位半占空比时钟，每个相位与其他时钟相位相差九十度; 将四个相位半占空比时钟耦合到四相半占空比混频器中; 以及四相半占空比混频器中的开关开关，以响应于四个相位半占空比时钟，以将差分输入信号与四个相位半占空比时钟进行并入，以同时产生差分同相输出信号和差分正交输出信号， 双差分输出端口的相位输出信号。

公开(公告)号：US20070236281A1

公开(公告)日：2007-10-11

申请号：US11399987

申请日：2006-04-07

申请人： Alberto Cicalini

发明人： Alberto Cicalini

IPC分类号： H03B1/00

CPC分类号： H03H1/02 ,  H03H2210/021 ,  H03H2210/043

摘要： A two-step tuning process for resistors and capacitors in an integrated circuit is described. In the first step of the tuning process, an on-chip adjustable resistor is tuned based on an external resistor to obtain a tuned resistor. The value of the tuned resistor is accurate to within a target percentage determined by the external resistor and the design of the adjustable resistor. In the second step, an adjustable capacitor is tuned based on the tuned resistor and an accurate clock to obtain a tuned capacitor having an accurate value. The adjustable capacitor may be tuned such that an RC time constant for the tuned resistor and the tune capacitor is accurate to within a target percentage determined by the accurate clock and the design of the adjustable capacitor. The resistors and capacitors of other circuits on the integrated circuit may be adjusted based on the tuned resistor and the tuned capacitor, respectively.

摘要翻译： 描述了集成电路中的电阻器和电容器的两步调谐过程。 在调谐过程的第一步中，基于外部电阻器调整片上可调电阻以获得调谐电阻。 调谐电阻的值精确到由外部电阻确定的目标百分比和可调电阻的设计之内。 在第二步中，基于调谐电阻器和精确时钟来调节可调电容器以获得具有准确值的调谐电容器。 可调整的可调电容器可以使得调谐电阻器和调谐电容器的RC时间常数精确到由精确时钟和可调电容器的设计确定的目标百分比之内。 可以分别基于调谐电阻器和调谐电容器来调整集成电路上的其它电路的电阻器和电容器。