公开(公告)号：US20100306557A1

公开(公告)日：2010-12-02

申请号：US12548063

申请日：2009-08-26

Applicant: QI-JIE CHEN

Inventor： QI-JIE CHEN

IPC: G06F1/00

CPC classification number: G06F1/3215

Abstract: A computer wake up circuit includes a first control circuit and a second control circuit. The first control circuit has an input terminal configured to receive a first control signal from a first serial device, and an output terminal coupled to a south bridge which is capable of waking up a computer. The second control circuit has an input terminal respectively coupled to a second serial device and an I/O controller, and an output terminal coupled to the south bridge. The second control circuit receives a second control signal from the second serial device. The first and second control circuits respectively outputs a wake up signal to the south bridge to wake up the computer according to the control signals. The I/O controller communicates with the second serial device through the second control circuit, and outputs other control signals to control operations of the second serial device.

Abstract translation: 计算机唤醒电路包括第一控制电路和第二控制电路。 第一控制电路具有被配置为从第一串行设备接收第一控制信号的输入端子和耦合到能够唤醒计算机的南桥的输出端子。 第二控制电路具有分别耦合到第二串行设备和I / O控制器的输入端子以及耦合到南桥的输出端子。 第二控制电路从第二串行装置接收第二控制信号。 第一和第二控制电路分别向南桥输出唤醒信号，以根据控制信号唤醒计算机。 I / O控制器通过第二控制电路与第二串行设备通信，并输出其他控制信号以控制第二串行设备的操作。

公开(公告)号：US20100309632A1

公开(公告)日：2010-12-09

申请号：US12556387

申请日：2009-09-09

Applicant: QI-JIE CHEN

Inventor： QI-JIE CHEN

IPC: H05K7/20

CPC classification number: H01L23/34 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/0215 ,  H05K1/116 ,  H05K3/325 ,  H05K3/42 ,  H05K2201/10409 ,  H01L2924/00

Abstract: A motherboard includes a printed circuit board, and a heat generating component mounted on the printed circuit board. A plurality of mounting holes is defined in the printed circuit board for mounting a heat sink apparatus on the heat generating component. At least a ground via is defined in the printed circuit board and adjacent to each of the mounting holes. The heat sink apparatus is capable of electrically contacting the ground via, and the ground via is capable of reducing electromagnetic interference of the motherboard and grounding static electricity on the heat sink apparatus.

Abstract translation: 主板包括印刷电路板和安装在印刷电路板上的发热部件。 在印刷电路板中限定了多个安装孔，用于将散热装置安装在发热部件上。 在印刷电路板中限定了至少一个接地孔，并且与每个安装孔相邻。 散热装置能够电接触地面通孔，并且接地通孔能够减少主板的电磁干扰并且在散热装置上接地静电。

公开(公告)号：US20100313049A1

公开(公告)日：2010-12-09

申请号：US12556786

申请日：2009-09-10

Applicant: QI-JIE CHEN

Inventor： QI-JIE CHEN

IPC: G06F1/26

CPC classification number: H03K17/28 ,  G06F1/3203

Abstract: A circuit for confirming a correct computer power down sequence includes a Southbridge chip, a first switching transistor circuit, and a second switching transistor circuit. The first switching transistor circuit receives a power good signal. The second switching transistor circuit receives a S3 sleep signal. The first and second switching transistor circuits have a common output node coupled to the Southbridge chip. During a computer power down sequence, the S3 sleep signal is set from high to low before than the power good signal, and the S3 sleep signal is active and fed to the Southbridge chip, thereby quickly providing a low level power good signal to the Southbridge chip and confirming the power down sequence is correct.

Abstract translation: 用于确认正确的计算机断电序列的电路包括南桥芯片，第一开关晶体管电路和第二开关晶体管电路。 第一开关晶体管电路接收电力良好信号。 第二开关晶体管电路接收S3睡眠信号。 第一和第二开关晶体管电路具有耦合到南桥芯片的公共输出节点。 在计算机断电序列期间，S3休眠信号从电源良好信号之前的高电平设置为低电平，S3睡眠信号被激活并馈送到南桥芯片，从而快速向南桥提供低电平电力良好信号 芯片并确认掉电顺序是正确的。

公开(公告)号：US20100306562A1

公开(公告)日：2010-12-02

申请号：US12508178

申请日：2009-07-23

Applicant: QI-JIE CHEN

Inventor： QI-JIE CHEN

IPC: G06F1/26

CPC classification number: G06F1/26

Abstract: A circuit for a computer system, includes a pulse width module (PWM) module and a control circuit. The PWM module is capable of converting a first voltage to a second voltage. The first voltage is capable of decreasing slower than the second voltage to have the PWM module entering in an unwanted state when the computer system is changed from a first state to a second state. The PWM module includes a disabling pin capable of locking the PWM module when a voltage of the disabling pin is low. The control circuit includes a control pin connected to the disabling pin, a ground pin connected to ground, and a monitoring pin capable of monitoring the computer system being changed from a first state to a second state to control the control pin and the ground pin to pull the disabling pin low to lock the PWM module to prevent the PWM module from entering in the unwanted state.

Abstract translation: 一种用于计算机系统的电路，包括脉冲宽度模块（PWM）模块和控制电路。 PWM模块能够将第一电压转换为第二电压。 当计算机系统从第一状态改变到第二状态时，第一电压能够比第二电压慢，以使PWM模块进入不期望的状态。 PWM模块包括禁用引脚，当禁用引脚的电压低时，该引脚能够锁定PWM模块。 所述控制电路包括连接到所述禁用引脚的控制引脚，连接到地的接地引脚和能够监视从第一状态改变到第二状态的计算机系统的监视引脚，以控制所述控制引脚和所述接地引脚 将禁用引脚拉低，锁定PWM模块，防止PWM模块进入不需要的状态。

公开(公告)号：US20100300732A1

公开(公告)日：2010-12-02

申请号：US12511286

申请日：2009-07-29

Applicant: QI-JIE CHEN

Inventor： QI-JIE CHEN

IPC: H05K1/02

CPC classification number: H05K1/0216 ,  H05K2201/09245 ,  H05K2201/097

Abstract: A multi-layer printed circuit board includes a first trace layer and a second trace layer. The second trace layer and the first trace layer are located on parallel horizontal planes. A first group of traces is laid on the first trace layer. A second group of traces is laid on the second trace layer. The second group of traces and the first group of traces are positioned on up and down positions of the first trace layer and the second trace layer. The first group of traces and the second group of traces extend in different directions.

Abstract translation: 多层印刷电路板包括第一迹线层和第二迹线层。 第二迹线层和第一迹线层位于平行水平面上。 第一组迹线放置在第一个迹线层上。 第二组轨迹铺设在第二个轨迹层上。 第二组迹线和第一组迹线位于第一迹线层和第二迹线层的上下位置。 第一组轨迹和第二组轨迹沿不同方向延伸。