公开(公告)号：US20220416761A1

公开(公告)日：2022-12-29

申请号：US17821906

申请日：2022-08-24

申请人： Qorvo US, Inc.

发明人： Alireza Tajic ,  Paul Stokes ,  Robert Aigner

IPC分类号： H03H9/13 ,  H01L41/047 ,  H03H9/02 ,  H03H9/17 ,  H01L41/053 ,  H03H9/54

摘要： Bulk acoustic wave (BAW) resonators, and particularly top electrodes with step arrangements for BAW resonators are disclosed. Top electrodes on piezoelectric layers are disclosed that include a border (BO) region with a dual-step arrangement where an inner step and an outer step are formed with increasing heights toward peripheral edges of the top electrode. Dielectric spacer layers may be provided between the outer steps and the piezoelectric layer. Passivation layers are disclosed that extend over the top electrode either to peripheral edges of the piezoelectric layer or that are inset from peripheral edges of the piezoelectric layer. Piezoelectric layers may be arranged with reduced thickness portions in areas that are uncovered by top electrodes. BAW resonators as disclosed herein are provided with high quality factors and suppression of spurious modes while also providing weakened BO modes that are shifted farther away from passbands of such BAW resonators.

公开(公告)号：US11502667B2

公开(公告)日：2022-11-15

申请号：US16525858

申请日：2019-07-30

申请人： Qorvo US, Inc.

发明人： Alireza Tajic ,  Paul Stokes ,  Robert Aigner

IPC分类号： H03H9/13 ,  H01L41/047 ,  H03H9/02 ,  H03H9/17 ,  H01L41/053 ,  H03H9/54

摘要： Bulk acoustic wave (BAW) resonators, and particularly top electrodes with step arrangements for BAW resonators are disclosed. Top electrodes on piezoelectric layers are disclosed that include a border (BO) region with a dual-step arrangement where an inner step and an outer step are formed with increasing heights toward peripheral edges of the top electrode. Dielectric spacer layers may be provided between the outer steps and the piezoelectric layer. Passivation layers are disclosed that extend over the top electrode either to peripheral edges of the piezoelectric layer or that are inset from peripheral edges of the piezoelectric layer. Piezoelectric layers may be arranged with reduced thickness portions in areas that are uncovered by top electrodes. BAW resonators as disclosed herein are provided with high quality factors and suppression of spurious modes while also providing weakened BO modes that are shifted farther away from passbands of such BAW resonators.

公开(公告)号：US11063021B2

公开(公告)日：2021-07-13

申请号：US16527702

申请日：2019-07-31

申请人： Qorvo US, Inc.

发明人： Julio C. Costa ,  Robert Aigner ,  Gernot Fattinger ,  Dirk Robert Walter Leipold ,  George Maxim ,  Baker Scott ,  Merrill Albert Hatcher, Jr. ,  Jon Chadwick

IPC分类号： H01L25/065 ,  H01L23/31 ,  H01L21/768 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L21/306

摘要： The present disclosure relates to a microelectronics package with vertically stacked flip-chip dies, and a process for making the same. The disclosed microelectronics package includes a module board, a first thinned flip-chip die with a through-die via, a second flip-chip die with a package contact at the bottom, and a mold compound. Herein, a top portion of the through-die via is exposed at top of the first thinned flip-chip die. The first thinned flip-chip die and the mold compound reside over the module substrate. The mold compound surrounds the first thinned flip-chip die and extends above the first thinned flip-chip die to define an opening. The second flip-chip die, which has a smaller plane size than the first thinned flip-chip die, resides within the opening and is stacked with the first thinned flip-chip die by coupling the package contact to the exposed top portion of the through-die via.

公开(公告)号：US20210183693A1

公开(公告)日：2021-06-17

申请号：US17121194

申请日：2020-12-14

申请人： Qorvo US, Inc.

发明人： Julio C. Costa ,  Robert Aigner

IPC分类号： H01L21/762 ,  H01L21/786 ,  H01L21/683 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

摘要： The present disclosure relates to a radio frequency device and a process for making the same. According to the process, a precursor wafer, which includes device regions, individual interfacial layers formed of SiGe, and a silicon handle substrate, is first provided. Each individual interfacial layer is over an active layer of a corresponding device region, and the silicon handle substrate is over each individual interfacial layer. A first bonding layer is formed underneath the precursor wafer. The precursor wafer is then attached to a support carrier with a second bonding layer. The first bonding layer and the second bonding layer merge to form a bonding structure between the precursor wafer and the support carrier. Next, the silicon handle substrate is removed from the precursor wafer to provide an etched wafer, and a first mold compound is applied to the etched wafer to provide a mold device wafer.

公开(公告)号：US11011498B2

公开(公告)日：2021-05-18

申请号：US16527702

申请日：2019-07-31

申请人： Qorvo US, Inc.

发明人： Julio C. Costa ,  Robert Aigner ,  Gernot Fattinger ,  Dirk Robert Walter Leipold ,  George Maxim ,  Baker Scott ,  Merrill Albert Hatcher, Jr. ,  Jon Chadwick

IPC分类号： H01L25/065 ,  H01L23/31 ,  H01L21/768 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L21/306

摘要： The present disclosure relates to a microelectronics package with vertically stacked flip-chip dies, and a process for making the same. The disclosed microelectronics package includes a module board, a first thinned flip-chip die with a through-die via, a second flip-chip die with a package contact at the bottom, and a mold compound. Herein, a top portion of the through-die via is exposed at top of the first thinned flip-chip die. The first thinned flip-chip die and the mold compound reside over the module substrate. The mold compound surrounds the first thinned flip-chip die and extends above the first thinned flip-chip die to define an opening. The second flip-chip die, which has a smaller plane size than the first thinned flip-chip die, resides within the opening and is stacked with the first thinned flip-chip die by coupling the package contact to the exposed top portion of the through-die via.

公开(公告)号：US10958245B2

公开(公告)日：2021-03-23

申请号：US15697658

申请日：2017-09-07

申请人： Qorvo US, Inc.

发明人： Nadim Khlat ,  Robert Aigner

IPC分类号： H03H9/58 ,  H03H9/13 ,  H03H9/00 ,  H03H9/60

摘要： A filter circuit includes a first input node and a second input node for receiving an input signal, and a first output node and a second output node for providing an output signal. A first series acoustic resonator is coupled in series between the first input node and the first output node. At least one coupled resonator filter (CRF) includes first and second transducers, which may be acoustically coupled to one another. The first transducer has a first electrode coupled to the first input node, a second electrode coupled to the second input node, and a first piezoelectric layer between the first electrode and the second electrode. A second transducer has a third electrode coupled to the first output node, a fourth electrode coupled to the second output node, and a second piezoelectric layer between the third electrode and the fourth electrode.

公开(公告)号：US10804246B2

公开(公告)日：2020-10-13

申请号：US16004961

申请日：2018-06-11

申请人： Qorvo US, Inc.

发明人： Julio C. Costa ,  Robert Aigner ,  Gernot Fattinger ,  Dirk Robert Walter Leipold ,  George Maxim ,  Baker Scott ,  Merrill Albert Hatcher, Jr. ,  Jon Chadwick

IPC分类号： H01L23/522 ,  H01L25/065 ,  H01L21/306 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00

摘要： The present disclosure relates to a microelectronics package with vertically stacked flip-chip dies, and a process for making the same. The disclosed microelectronics package includes a module board, a first thinned flip-chip die with a through-die via, a second flip-chip die with a package contact at the bottom, and a mold compound. Herein, a top portion of the through-die via is exposed at top of the first thinned flip-chip die. The first thinned flip-chip die and the mold compound reside over the module substrate. The mold compound surrounds the first thinned flip-chip die and extends above the first thinned flip-chip die to define an opening. The second flip-chip die, which has a smaller plane size than the first thinned flip-chip die, resides within the opening and is stacked with the first thinned flip-chip die by coupling the package contact to the exposed top portion of the through-die via.

公开(公告)号：US20190334498A1

公开(公告)日：2019-10-31

申请号：US16507678

申请日：2019-07-10

申请人： Qorvo US, Inc.

发明人： Shogo Inoue ,  Marc Solal ,  Robert Aigner

IPC分类号： H03H3/02 ,  H03H3/10 ,  H03H9/02 ,  H03H9/64 ,  H03H9/54 ,  H03H9/25 ,  H03H9/17 ,  H03H9/145

摘要： A method of fabricating a bonded wafer with low carrier lifetime in silicon comprises providing a silicon substrate having opposing top and bottom surfaces, modifying a top portion of the silicon substrate to reduce carrier lifetime in the top portion relative to the carrier lifetime in portions of the silicon substrate other than the top portion, bonding a piezoelectric layer having opposing top and bottom surfaces separated by a distance T over the top surface of the silicon substrate, and providing a pair of electrodes having fingers that are inter-digitally dispersed on a top surface of the piezoelectric layer, the electrodes comprising a portion of a Surface Acoustic Wave (SAW) device. The modifying and bonding steps may be performed in any order. The modified top portion of the silicon substrate prevents the creation of a parasitic conductance within that portion during operation of the SAW device.

公开(公告)号：US20190222197A1

公开(公告)日：2019-07-18

申请号：US16358823

申请日：2019-03-20

申请人： Qorvo US, Inc.

发明人： Nadim Khlat ,  Robert Aigner

IPC分类号： H03H9/52 ,  H03H9/56 ,  H03H9/205

CPC分类号： H03H9/52 ,  H03H9/205 ,  H03H9/568 ,  H03H9/584 ,  H03H9/589 ,  H03H9/605

摘要： A zero-output coupled resonator filter (ZO-CRF) and related radio frequency (RF) filter circuit are provided. In examples discussed herein, the ZO-CRF can be configured to function as a shunt resonator(s) in an RF filter circuit (e.g., a ladder filter circuit). The ZO-CRF includes a first resonator and a second resonator that are coupled to each other via a coupling layer. The first resonator and the second resonator receive a first voltage and a second voltage, respectively. The first voltage and the second voltage can be configured in a number of ways to cause the ZO-CRF to resonate at different resonance frequencies. As such, it may be possible to modify resonance frequency of the ZO-CRF in an RF filter circuit based on signal connection. As a result, it may be possible to reduce total inductance of the RF filter circuit, thus helping to reduce footprint of the RF filter circuit.

公开(公告)号：US20240027576A1

公开(公告)日：2024-01-25

申请号：US18348552

申请日：2023-07-07

申请人： Qorvo US, Inc.

发明人： Nadim Khlat ,  Robert Aigner

IPC分类号： G01S7/28 ,  G01S13/02 ,  G01S13/04

CPC分类号： G01S7/2806 ,  G01S13/0209 ,  G01S13/04

摘要： A wireless device operable to detect a nearby object is disclosed. Herein, an object is considered a nearby object when a roundtrip propagation duration of a pulse(s) between an antenna and the object is less than two nanoseconds (2 ns). Given the close proximity of the object, an echo of the emitted pulse(s) may be reflected instantaneously toward the antenna to potentially overlap with the emitted pulse(s), thus causing difficulty in detecting the reflected pulse(s). In this regard, in embodiments disclosed herein, an acoustic delay circuit is provided in the wireless device to add a temporal delay in the emitted pulse(s) and the reflected pulse(s) to prevent the reflected pulse(s) from overlapping with the emitted pulse(s). As a result, the wireless device can accurately receive the reflected pulse(s) to thereby detect the nearby object.