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公开(公告)号:US20240339928A1
公开(公告)日:2024-10-10
申请号:US18605031
申请日:2024-03-14
申请人: Qorvo US, Inc.
发明人: Baker Scott , George Maxim , Nadim Khlat , Hui Liu , David Edward Reed , Christopher T. Brown
CPC分类号: H02M3/156 , H02M1/0009
摘要: Systems and methods for providing a direct current-to-direct current (DC-DC) converter with programmable compensation are disclosed. In one aspect, a power management chip having a DC-DC converter measures process, voltage, and temperature (PVT) variations and provides a dynamic compensation circuit (e.g., using programmable digital-to-analog converters (DACs)) to offset such PVT variations. Further, changes in frequency may be detected, and additional compensation values provided. Providing compensation in this manner allows the DC-DC converter's performance to be more efficient, resulting in better performance and power savings.
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公开(公告)号:US20240339918A1
公开(公告)日:2024-10-10
申请号:US18616740
申请日:2024-03-26
申请人: Qorvo US, Inc.
发明人: Baker Scott , George Maxim , Nadim Khlat , Hui Liu , David Edward Reed
CPC分类号: H02M1/0048 , H02M1/44 , H02M3/155
摘要: Systems and methods for improving efficiency in a power management circuit are disclosed. In one aspect, a ping-pong sample and hold circuit smooth transitions from buck to boost (and vice versa) modes of operation for a direct current-to-direct current (DC-DC) converter in the power management circuit. The ping-pong sample and hold circuit provide a ramp compensation for each clock cycle, where transitions are smoothed by holding the last value used from the previous mode of operation. In a second aspect, a current sensor is used that integrates a current value to provide a base feedback loop for the DC-DC converter and may use various compensation factors to provide a proper ramp signal for the DC-DC converter.
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公开(公告)号:US20240030117A1
公开(公告)日:2024-01-25
申请号:US18254162
申请日:2021-12-13
申请人: Qorvo US, Inc.
发明人: Julio C. Costa , George Maxim , Baker Scott
IPC分类号: H01L23/498 , H01L23/00 , H01L25/065
CPC分类号: H01L23/49816 , H01L23/49822 , H01L24/16 , H01L25/0657 , H01L24/32 , H01L24/73 , H01L2224/73253 , H01L2224/16235 , H01L2224/16146 , H01L2224/32235 , H01L2224/32146 , H01L2225/06517 , H01L2225/06586 , H01L2924/182 , H01L2924/15321
摘要: The present disclosure relates to a multi-level three-dimensional (3D) package with multiple package levels vertically stacked. Each package level includes a redistribution structure and a die section over the redistribution structure. Each die section includes a thinned die that includes substantially no silicon substrate and has a thickness between several micrometers and several tens of micrometers, a mold compound, and an intermediary mold compound. Herein, the thinned die and the mold compound are deposed over the redistribution structure, the mold compound surrounds the thinned die and extends vertically beyond a top surface of the thinned die to define an opening over the thinned die and within the mold compound, the intermediary mold compound resides over the thinned die and fills the opening within the inner mold compound, such that a top surface of the intermediary mold compound and a top surface of the mold compound are coplanar.
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公开(公告)号:US20230246599A1
公开(公告)日:2023-08-03
申请号:US17589050
申请日:2022-01-31
申请人: Qorvo US, Inc.
发明人: Baker Scott , Chong Woo , George Maxim
CPC分类号: H03F1/302 , H03F3/245 , H03F2200/451 , H03F2200/447
摘要: A power amplifier with feedback ballast resistance is disclosed. In one aspect, a power amplifier cell may receive a bias signal from a bias circuit where the bias circuit includes a feedback loop having an impedance that, from the perspective of the bias signal is relatively low impedance, but from a ballast thermal control perspective provides sufficient resistance to avoid thermal runaway. In exemplary aspects, this feedback loop may be extended to operate with multiple power amplifier cells and provide differential mode thermal control optimized for individual cell bias signal control and common mode thermal control optimized for thermal control of the collective power amplifier cells of the power amplifier.
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公开(公告)号:US11626892B1
公开(公告)日:2023-04-11
申请号:US17665687
申请日:2022-02-07
申请人: Qorvo US, Inc.
发明人: George Maxim , Baker Scott , Ali Tombak
摘要: A multi-band radio frequency (RF) front-end circuit is provided. The multi-band RF front-circuit includes multiple RF circuits configured to amplify RF signals received and/or to be transmitted in multiple RF bands and/or polarizations via an antenna circuit. The antenna circuit includes multiple antenna tap points each coupled to a respective one of the RF circuits. Since each of the RF circuits has a respective impedance that can vary based on the RF bands, the antenna tap points are so positioned on the antenna circuit to each present a respective drive impedance that matches the respective impedance of a coupled RF circuit. Further, the antenna tap points are also positioned on the antenna circuit to cause desired RF isolations between the RF bands and/or the polarizations. Consequently, the multi-band RF front-end circuit can achieve optimal RF performance across a wide range of RF bands with reduced footprint and insertion losses.
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公开(公告)号:US20230094883A1
公开(公告)日:2023-03-30
申请号:US17488823
申请日:2021-09-29
申请人: Qorvo US, Inc.
发明人: Baker Scott , Stephen James Franck , George Maxim , Chong Woo
摘要: A power amplifier includes an over-current protection loop and/or an over-voltage protection loop to assist in preventing operation outside a safe operation zone. In a further exemplary aspect, triggering of the over-current protection loop adjusts a threshold voltage for the over-voltage protection loop. In further exemplary aspects, the over-current protection loop may adjust not only a bias regulator, but also provide an auxiliary control signal that further limits signals reaching the power amplifier. In still further exemplary aspects, the over-voltage protection loop may operate independently of the over-current protection current loop or the over-voltage protection loop contribute to an over-current protection signal.
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公开(公告)号:US11476177B2
公开(公告)日:2022-10-18
申请号:US16204214
申请日:2018-11-29
申请人: Qorvo US, Inc.
发明人: Julio C. Costa , George Maxim
IPC分类号: H01L23/28 , H01L23/48 , H01L23/52 , H01L23/36 , H01L23/31 , H01L23/482 , H01L23/495 , H01L23/498 , H05K1/02
摘要: The present disclosure relates to a thermally enhanced package, which includes a carrier, a thinned die over the carrier, a mold compound, and a heat extractor. The thinned die includes a device layer over the carrier and a dielectric layer over the device layer. The mold compound resides over the carrier, surrounds the thinned die, and extends beyond a top surface of the thinned die to define an opening within the mold compound and over the thinned die. The top surface of the thinned die is at a bottom of the opening. At least a portion of the heat extractor is inserted into the opening and in thermal contact with the thinned die. Herein the heat extractor is formed of a metal or an alloy.
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公开(公告)号:US11443999B2
公开(公告)日:2022-09-13
申请号:US16204214
申请日:2018-11-29
申请人: Qorvo US, Inc.
发明人: Julio C. Costa , George Maxim
IPC分类号: H01L23/28 , H01L23/48 , H01L23/52 , H01L23/36 , H01L23/31 , H01L23/482 , H01L23/495 , H01L23/498 , H05K1/02
摘要: The present disclosure relates to a thermally enhanced package, which includes a carrier, a thinned die over the carrier, a mold compound, and a heat extractor. The thinned die includes a device layer over the carrier and a dielectric layer over the device layer. The mold compound resides over the carrier, surrounds the thinned die, and extends beyond a top surface of the thinned die to define an opening within the mold compound and over the thinned die. The top surface of the thinned die is at a bottom of the opening. At least a portion of the heat extractor is inserted into the opening and in thermal contact with the thinned die. Herein the heat extractor is formed of a metal or an alloy.
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公开(公告)号:US11244786B2
公开(公告)日:2022-02-08
申请号:US16555281
申请日:2019-08-29
申请人: Qorvo US, Inc.
摘要: This disclosure relates generally to substrates having three dimensional (3D) inductors and methods of manufacturing the same. In one embodiment, the 3D inductor is a solenoid inductor where the exterior edge contour of the winding ends is substantially the same and substantially aligned with the exterior edge contour of the exterior edge contour of conductive vias that connect the windings. In this manner, there is no overhang between the windings and the conductive vias. In another embodiment of the 3D inductor, via columns connect connector plates. The via column attachment surfaces of each of the conductive vias in each of the columns is the same and substantially aligned. In this manner, carrier pads are not needed and there is no overhand between the conductive vias.
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公开(公告)号:US11177064B2
公开(公告)日:2021-11-16
申请号:US16590449
申请日:2019-10-02
申请人: Qorvo US, Inc.
IPC分类号: H01F27/28 , H01F17/00 , H03F1/56 , H03F3/193 , H03F3/24 , H03F3/68 , H03F3/72 , H04B1/525 , H03H7/09 , H03H7/01
摘要: Embodiments of an apparatus that includes a substrate and an inductor residing in the substrate are disclosed. In one embodiment, the inductor is formed as a conductive path that extends from a first terminal to a second terminal. The conductive path has a shape corresponding to a two-dimensional (2D) lobe laid over a three-dimensional (3D) volume. Since the shape of the conductive path corresponds to the 2D lobe laid over a 3D volume, the magnetic field generated by the inductor has magnetic field lines that are predominately destructive outside the inductor and magnetic field lines that are predominately constructive inside the inductor. In this manner, the inductor can maintain a high quality (Q) factor while being placed close to other components.
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