公开(公告)号：US11934219B2

公开(公告)日：2024-03-19

申请号：US17707621

申请日：2022-03-29

Applicant: QUALCOMM Incorporated

Inventor： Arvind Jain ,  Divya Gangadharan ,  Muhammad Nasir ,  Hong Dai ,  Madan Krishnappa

IPC: G06F1/06 ,  G01R31/317 ,  H04B1/401

CPC classification number: G06F1/06 ,  G01R31/31727 ,  H04B1/401

Abstract: An aspect of the disclosure relates to an integrated circuit (IC). The IC includes a first set of test clock controllers (TCCs) including a first set of clock outputs, respectively; and a first set of functional cores including a first set of clock inputs coupled to the first set of clock outputs of the first set of TCCs, respectively.

公开(公告)号：US20180340977A1

公开(公告)日：2018-11-29

申请号：US15603779

申请日：2017-05-24

Applicant: QUALCOMM Incorporated

Inventor： Tapan Jyoti Chakraborty ,  Alvin Leng Sun Loke ,  Hong Dai ,  Thomas Clark Bryan

IPC: G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/318505 ,  G01R31/318513 ,  G01R31/318533 ,  G01R31/318536

Abstract: Test architectures for multi-die chips are provided herein according to embodiments of the present disclosure. In certain aspects, an exemplary test architecture enables an external tester to perform various tests on a multi-die chip that includes multiple dies. In a first test mode, the test architecture enables the external tester to currently perform die-level tests on the multiple dies. In a second test mode, the test architecture enables the external tester to perform a chip-level test on the multi-die chip. The chip-level test may include die-to-die tests for testing interconnections between the multiple dies on the multi-die chip. The chip-level test may also include a boundary input/output (I/O) test for testing external connections between the multi-die chip and one or more devices external to the multi-die chip.

公开(公告)号：US12300337B2

公开(公告)日：2025-05-13

申请号：US17944691

申请日：2022-09-14

Applicant: QUALCOMM INCORPORATED

Inventor： Hong Dai ,  Amir Borovietzky ,  Arvind Jain ,  Massine Bitam ,  Madan Krishnappa

IPC: G11C29/32 ,  G01R31/319 ,  G11C29/44

Abstract: A system for repairing a random access memory may include serial test interface logic, fuse-sense logic, a repair data register chain, and multiplexing logic. The repair data register chain may include serially interconnected data registers configured to shift data through the repair data register chain. Each data register of the repair data register chain may have a data output configured to be coupled to a repair information input of the random access memory. The multiplexing logic may be configured to provide a soft-repair mode and a hard-repair mode. When the soft-repair mode is selected, the multiplexing logic may be configured to receive soft-repair data provided by the serial test interface logic into the data registers. When the hard-repair mode is selected, the multiplexing logic may be configured to receive the data provided by the fuse-sense logic into the data registers.

公开(公告)号：US10429441B2

公开(公告)日：2019-10-01

申请号：US15603779

申请日：2017-05-24

Applicant: QUALCOMM Incorporated

Inventor： Tapan Jyoti Chakraborty ,  Alvin Leng Sun Loke ,  Hong Dai ,  Thomas Clark Bryan

IPC: G01R31/3177 ,  G01R31/317 ,  G01R31/3185

Abstract: Test architectures for multi-die chips are provided herein according to embodiments of the present disclosure. In certain aspects, an exemplary test architecture enables an external tester to perform various tests on a multi-die chip that includes multiple dies. In a first test mode, the test architecture enables the external tester to currently perform die-level tests on the multiple dies. In a second test mode, the test architecture enables the external tester to perform a chip-level test on the multi-die chip. The chip-level test may include die-to-die tests for testing interconnections between the multiple dies on the multi-die chip. The chip-level test may also include a boundary input/output (I/O) test for testing external connections between the multi-die chip and one or more devices external to the multi-die chip.