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    Zero-pin test solution for integrated circuits
    1.
    发明授权
    Zero-pin test solution for integrated circuits 有权

    公开(公告)号：US11041904B2

    公开(公告)日：2021-06-22

    申请号：US16589968

    申请日：2019-10-01

    Applicant: QUALCOMM Incorporated

    Inventor： Tapan Jyoti Chakraborty ,  Umesh Srikantiah ,  Rachana Rout

    IPC: G01R31/317 ,  G01R31/3177

    Abstract: In some aspects, the present disclosure provides a method for testing an integrated circuit (IC). In some configurations, the method includes determining, by a test controller embedded in the IC, a change in operation of the IC from a normal mode to a test mode. The method also includes communicating, by the test controller to a chain of data storage elements in the IC: a first test signal configured to change an input/output (I/O) function of a first IC pin, and a second test signal configured to apply one of a plurality of test functions to each data storage element in the chain of data storage elements. The method also includes, receiving, via a second IC pin, a test clock signal configured to control a latch function of each data storage element in the chain of data storage elements.

    Embedded memory testing with storage borrowing
    3.
    发明授权
    Embedded memory testing with storage borrowing 有权

    公开(公告)号：US10249380B2

    公开(公告)日：2019-04-02

    申请号：US15418543

    申请日：2017-01-27

    Applicant: QUALCOMM Incorporated

    Inventor： Tapan Jyoti Chakraborty ,  Roberto Fabian Averbuj

    IPC: G11C29/12 ,  G01R31/28 ,  G11C29/02 ,  G11C29/04 ,  G11C29/38 ,  G11C29/44 ,  G11C29/32

    Abstract: An integrated circuit (IC) is disclosed herein for embedded memory testing with storage borrowing. In an example aspect, an integrated circuit includes a functional logic block, a memory block, and test logic. The functional logic block includes multiple storage units and is configured to store functional data in the multiple storage units during a regular operational mode. The test logic is configured to perform a test on the memory block during a testing mode. The test logic is also configured to retain memory test result data in the multiple storage units of the functional logic block during the testing mode.

    Efficient test architecture for multi-die chips
    4.
    发明授权
    Efficient test architecture for multi-die chips 有权

    公开(公告)号：US10429441B2

    公开(公告)日：2019-10-01

    申请号：US15603779

    申请日：2017-05-24

    Applicant: QUALCOMM Incorporated

    Inventor： Tapan Jyoti Chakraborty ,  Alvin Leng Sun Loke ,  Hong Dai ,  Thomas Clark Bryan

    IPC: G01R31/3177 ,  G01R31/317 ,  G01R31/3185

    Abstract: Test architectures for multi-die chips are provided herein according to embodiments of the present disclosure. In certain aspects, an exemplary test architecture enables an external tester to perform various tests on a multi-die chip that includes multiple dies. In a first test mode, the test architecture enables the external tester to currently perform die-level tests on the multiple dies. In a second test mode, the test architecture enables the external tester to perform a chip-level test on the multi-die chip. The chip-level test may include die-to-die tests for testing interconnections between the multiple dies on the multi-die chip. The chip-level test may also include a boundary input/output (I/O) test for testing external connections between the multi-die chip and one or more devices external to the multi-die chip.

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