公开(公告)号：US10481202B2

公开(公告)日：2019-11-19

申请号：US15835227

申请日：2017-12-07

Applicant: QUALCOMM Incorporated

Inventor： Arvind Jain ,  Nishi Bhushan Singh ,  Rahul Gulati ,  Pranjal Bhuyan ,  Rakesh Kumar Kinger ,  Roberto Averbuj

IPC: G01R31/317 ,  G01R31/3187 ,  G01R31/319 ,  G01R31/3183 ,  G01R31/3185 ,  G06F9/448

Abstract: A self-test controller includes a memory configured to store a test patterns, configuration registers, and a memory data component. The test patterns are encoded in the memory using various techniques in order to save storage space. By using the configuration parameters, the memory data component is configured to decode the test patterns and perform multiple built-in self-test on a multitude of test cores. The described techniques allow for built-in self-test to be performed dynamically while utilizing less space in the memory.

公开(公告)号：US12300337B2

公开(公告)日：2025-05-13

申请号：US17944691

申请日：2022-09-14

Applicant: QUALCOMM INCORPORATED

Inventor： Hong Dai ,  Amir Borovietzky ,  Arvind Jain ,  Massine Bitam ,  Madan Krishnappa

IPC: G11C29/32 ,  G01R31/319 ,  G11C29/44

Abstract: A system for repairing a random access memory may include serial test interface logic, fuse-sense logic, a repair data register chain, and multiplexing logic. The repair data register chain may include serially interconnected data registers configured to shift data through the repair data register chain. Each data register of the repair data register chain may have a data output configured to be coupled to a repair information input of the random access memory. The multiplexing logic may be configured to provide a soft-repair mode and a hard-repair mode. When the soft-repair mode is selected, the multiplexing logic may be configured to receive soft-repair data provided by the serial test interface logic into the data registers. When the hard-repair mode is selected, the multiplexing logic may be configured to receive the data provided by the fuse-sense logic into the data registers.

公开(公告)号：US11934219B2

公开(公告)日：2024-03-19

申请号：US17707621

申请日：2022-03-29

Applicant: QUALCOMM Incorporated

Inventor： Arvind Jain ,  Divya Gangadharan ,  Muhammad Nasir ,  Hong Dai ,  Madan Krishnappa

IPC: G06F1/06 ,  G01R31/317 ,  H04B1/401

CPC classification number: G06F1/06 ,  G01R31/31727 ,  H04B1/401

Abstract: An aspect of the disclosure relates to an integrated circuit (IC). The IC includes a first set of test clock controllers (TCCs) including a first set of clock outputs, respectively; and a first set of functional cores including a first set of clock inputs coupled to the first set of clock outputs of the first set of TCCs, respectively.

公开(公告)号：US11037651B2

公开(公告)日：2021-06-15

申请号：US16675676

申请日：2019-11-06

Applicant: QUALCOMM Incorporated

Inventor： Arvind Jain ,  Anju George ,  Swayam Pattnaik

IPC: G11C29/00 ,  G11C29/56 ,  G11C29/48 ,  G11C29/14 ,  G11C29/32

Abstract: Disclosed are methods and apparatus for securely accessing and testing a double data rate (DDR) memory device. The apparatus includes a first memory test access port (TAP) configured to enable or disable access to at least one double date rate (DDR) memory device, a second memory TAP configured to enable or disable access to at least one non-DDR memory device, and a test controller configured to test the at least one DDR memory device via the first memory TAP or test the at least one non-DDR memory device via the second memory TAP. In an aspect, at least one non-DDR memory device contains proprietary information. Accordingly, access to the at least one non-DDR memory device via the second memory TAP is disabled when access to the at least one DDR memory device via the first memory TAP is enabled.