公开(公告)号：US20220137687A1

公开(公告)日：2022-05-05

申请号：US17085505

申请日：2020-10-30

Applicant: QUALCOMM INCORPORATED

Inventor： Christopher Kong Yee CHUN ,  Chandan AGARWALLA ,  Dipti Ranjan PAL ,  Kumar Kanti GHOSH ,  Matthew SEVERSON ,  Nilanjan BANERJEE ,  Joshua STUBBS

IPC: G06F1/26

Abstract: Dynamic power supply voltage adjustment in a computing device may involve two stages. In a first stage, a first method for adjusting a power supply voltage may be disabled. While the first method remains disabled, a request to adjust the power supply voltage from an initial value to a target value using a second method may be received. The second method may be initiated in response to the request if a time interval has elapsed since a previous request to adjust the power supply voltage. In a second stage, the first method may be enabled when it has been determined that the power supply voltage has reached the target value.

公开(公告)号：US20240201762A1

公开(公告)日：2024-06-20

申请号：US18082518

申请日：2022-12-15

Applicant: QUALCOMM Incorporated

Inventor： Aravind BHASKARA ,  Zhurang ZHAO ,  Kiran BHAGWAT ,  Michael TIPTON ,  Joshua STUBBS ,  Jyotirmoy DAS ,  Thomas TANG

IPC: G06F1/26 ,  G06F1/08

CPC classification number: G06F1/26 ,  G06F1/08

Abstract: Various dynamic voltage and frequency scaling (DVFS) techniques can optimize the high voltage residency of a device containing multiple processing cores that share a voltage rail. The DVFS techniques described herein can reduce the high voltage residency (duration) of the voltage rail by aligning the high frequency duration of multiple cores sharing the same voltage rail.

公开(公告)号：US20240276096A1

公开(公告)日：2024-08-15

申请号：US18165189

申请日：2023-02-06

Applicant: QUALCOMM Incorporated

Inventor： Aravind BHASKARA ,  Tauseef KAZI ,  Zhurang ZHAO ,  Rohan DESAI ,  Michael TIPTON ,  Joshua STUBBS ,  Kiran BHAGWAT ,  Pavan Kumar CHILAMKURTHI

IPC: H04N23/65 ,  H04N25/71

CPC classification number: H04N23/651 ,  H04N25/745

Abstract: Systems, methods, and computer-readable media are provided for camera dynamic voting to optimize fast sensor mode power. In some examples, a computing device can obtain, based on performing dynamic voting, a plurality of votes associated with a plurality of components sharing a power source. The computing device can determine a voting result based on the plurality of votes. The computing device can increase or decreasing a clock rate and a voltage for the power source based on the voting result to produce an updated clock rate and an updated voltage. The computing device can then apply the updated clock rate and the updated voltage to an image processor.