-
公开(公告)号：US20180329838A1
公开(公告)日：2018-11-15
申请号：US15960356
申请日：2018-04-23
Applicant: QUALCOMM Incorporated
Inventor： Lalan Jee MISHRA , Christopher Kong Yee CHUN , Richard Dominic WIETFELDT , Mohit Kishore PRASAD
IPC: G06F13/16
CPC classification number: G06F13/1605 , G06F13/1673 , G06F13/4291 , G06F2213/0016
Abstract: Systems, methods, and apparatus for communicating datagrams over a serial communication link are provided. A receiving device captures a sending device address during bus arbitration and receives a datagram subsequent to the bus arbitration. The datagram includes at least a register address and a payload. The receiving device obtains an address region specific to the sending device within a register space of the receiving device based on the captured sending device address and the register address included in the datagram and writes the payload of the datagram to the register space according to the obtained address region.
-
公开(公告)号：US20200073847A1
公开(公告)日：2020-03-05
申请号：US16678827
申请日：2019-11-08
Applicant: QUALCOMM Incorporated
Inventor： Lalan Jee MISHRA , Mohit Kishore PRASAD , Richard Dominic WIETFELDT , Christopher Kong Yee CHUN
Abstract: Systems, methods, and apparatus for communicating datagrams over a serial communication link are provided. A transmitting device generates an address field in a datagram, sets a value of at least one bit in the address field to indicate a number of bytes of data associated with a data frame of the datagram, generates the data frame in the datagram, the data frame including the number of bytes of data, and sends the datagram to a receiving device. A receiving device receives a datagram from a transmitting device, decodes an address field of the datagram to detect a number of bytes of data included in a data frame of the datagram based on a value of at least one bit in the address field, and decodes the data frame to recover the detected number of bytes of data.
-
公开(公告)号：US20190317911A1
公开(公告)日：2019-10-17
申请号：US16037802
申请日：2018-07-17
Applicant: QUALCOMM Incorporated
Abstract: Systems, methods, and apparatus for communicating a control signal between device components are provided. Within an apparatus, an integrated circuit (IC) sends a control signal to a system on chip (SoC). The control signal requests enablement or disablement of one or more resources corresponding to the IC. Thereafter, a converting circuit within the SoC converts the control signal from the IC into a command to be transmitted to one or more devices. The converting circuit then transmits the command to the one or more devices via a bus coupling the SoC to the one or more devices. The one or more devices includes one or more power management integrated circuits (PMICs) configured to control the one or more resources. As such, the one or more PMICs enable or disable the one or more resources corresponding to the IC based on the command
-
公开(公告)号：US20240281401A1
公开(公告)日：2024-08-22
申请号：US18171264
申请日：2023-02-17
Applicant: QUALCOMM Incorporated
Inventor： Lalan Jee MISHRA , Richard Dominic WIETFELDT , Umesh SRIKANTIAH , Francesco GATTA , Christopher Kong Yee CHUN
CPC classification number: G06F13/4282 , G06F13/4022 , G06F2213/0018
Abstract: A subordinate device participates in address assignment through iterative communication with a host device. The subordinate device receives a first broadcast command over a multidrop serial bus, decouples a daisy chain input of the subordinate device from a daisy chain output of the subordinate device, receives a second broadcast command over the multidrop serial bus, responds to the second broadcast command when a signal received through the daisy chain input is in an active state, ignores the second broadcast command when the signal received through the daisy chain input is in an inactive state, and ignores subsequent broadcast commands after responding to the second broadcast command. Responding to the second broadcast command includes configuring a unique device identifier of the subordinate device using an address provided in the second broadcast command, and coupling the daisy chain input of the subordinate device to the daisy chain output of the subordinate device.
-
公开(公告)号：US20190286587A1
公开(公告)日：2019-09-19
申请号：US16262267
申请日：2019-01-30
Applicant: QUALCOMM Incorporated
Inventor： Lalan Jee MISHRA , Richard Dominic WIETFELDT , Helena Deirdre O'SHEA , Wolfgang ROETHIG , Christopher Kong Yee CHUN , ZhenQi CHEN , Scott DAVENPORT , Chiew-Guan TAN , Wilson CHEN , Umesh SRIKANTIAH
Abstract: Systems, methods, and apparatus for data communication are provided. A method performed by a bus master includes terminating transmission of a first datagram by signaling a first bus park cycle on a serial bus, causing a driver to enter a high-impedance state, opening an interrupt window by providing a first edge in a clock signal transmitted on a second line of the serial bus, closing the interrupt window by providing a second edge in the clock signal, signaling a second bus park cycle on the serial bus, initiating an arbitration process when an interrupt was received on the first line of the serial bus while the interrupt window was open, and initiating a transmission of a second datagram when an interrupt was not received on the first line of the serial bus while the interrupt window was open.
-
Patent Agency Ranking
公开(公告)号：US20200233829A1
公开(公告)日：2020-07-23
申请号：US16254189
申请日：2019-01-22
Applicant: QUALCOMM Incorporated
Inventor： Dilin VALIPARAMBIL DIVAKAR , Christopher Kong Yee CHUN
Abstract: Systems, methods, and apparatus related to the operation of a multilane serial bus communicate the configuration of lanes used to handle a transaction over the serial bus through signaling transmitted at the commencement of the transaction. The method includes asserting a multilane bus request by initiating a pulse on a secondary data lane of the serial bus while the clock lane is idle, participating in a first bus arbitration procedure executed using the secondary data lane after the pulse is terminated, providing initial signaling on the secondary data lane after winning the first bus arbitration procedure to indicate a set of data lanes to be used during a transaction, and executing a first transaction using the set of data lanes. The set of data lanes may include the primary data lane and the secondary data lane. The initial signaling may include a sequence start condition.
-
公开(公告)号：US20180329856A1
公开(公告)日：2018-11-15
申请号：US15966687
申请日：2018-04-30
Applicant: QUALCOMM Incorporated
Inventor： Lalan Jee MISHRA , Mohit Kishore PRASAD , Richard Dominic WIETFELDT , Christopher Kong Yee CHUN
CPC classification number: G06F13/4282 , G06F13/102 , G06F13/1668 , G06F13/20
Abstract: Systems, methods, and apparatus for communicating datagrams over a serial communication link are provided. A transmitting device generates an address field in a datagram, sets a value of at least one bit in the address field to indicate a number of bytes of data associated with a data frame of the datagram, generates the data frame in the datagram, the data frame including the number of bytes of data, and sends the datagram to a receiving device. A receiving device receives a datagram from a transmitting device, decodes an address field of the datagram to detect a number of bytes of data included in a data frame of the datagram based on a value of at least one bit in the address field, and decodes the data frame to recover the detected number of bytes of data.
-
公开(公告)号：US20240403062A1
公开(公告)日：2024-12-05
申请号：US18327654
申请日：2023-06-01
Applicant: QUALCOMM Incorporated
Inventor： Christopher Kong Yee CHUN
IPC: G06F9/4401
Abstract: Aspects of the present disclosure are directed to techniques and apparatuses for implementing a power-on (PON) sequence in a computer system. A power management integrated circuit (PMIC) receives a boot circuit indicator (BCI) signal from a computer system. The BCI signal identifies a circuit of the computer system to be enabled in a power-on (PON) sequence. The PMIC provides power to the boot core or cluster of the SoC based on the BCI signal.
-
公开(公告)号：US20240334109A1
公开(公告)日：2024-10-03
申请号：US18194057
申请日：2023-03-31
Applicant: QUALCOMM Incorporated
Inventor： Vishal AGARWAL , Srivathsa SRIDHARA , Christopher Kong Yee CHUN
CPC classification number: H04R1/1025 , H04W52/028
Abstract: Various embodiments include systems and methods for balancing battery cycles of paired earbuds. A processor in an earbud charging case may receive battery level information from a first earbud operating in a deep sleep mode, determine a battery differential index (BDI) value, and send an instruction message to the first earbud indicating the first earbud should switch roles with a second earbud. An earbud may start a timer upon beginning to operate in a dormant mode, transition from operating in the dormant mode to operating in a non-dormant mode in response to expiration of the timer, send a message to a paired earbud indicating that the earbud has transitioned, and receive a message from the paired earbud indicating that the earbud should switch from operating in the dormant mode to operating in the deep sleep mode and periodically broadcasting an advertisement.
-
公开(公告)号：US20220137687A1
公开(公告)日：2022-05-05
申请号：US17085505
申请日：2020-10-30
Applicant: QUALCOMM INCORPORATED
Inventor： Christopher Kong Yee CHUN , Chandan AGARWALLA , Dipti Ranjan PAL , Kumar Kanti GHOSH , Matthew SEVERSON , Nilanjan BANERJEE , Joshua STUBBS
IPC: G06F1/26
Abstract: Dynamic power supply voltage adjustment in a computing device may involve two stages. In a first stage, a first method for adjusting a power supply voltage may be disabled. While the first method remains disabled, a request to adjust the power supply voltage from an initial value to a target value using a second method may be received. The second method may be initiated in response to the request if a time interval has elapsed since a previous request to adjust the power supply voltage. In a second stage, the first method may be enabled when it has been determined that the power supply voltage has reached the target value.
-
-
-
-
-
-
-
-
-
Search Results
11
records
(took 0.013 seconds)
