公开(公告)号：US20210065772A1

公开(公告)日：2021-03-04

申请号：US16945303

申请日：2020-07-31

Applicant: QUALCOMM Incorporated

Inventor： Jungwon SUH ,  Michael Hawjing LO ,  Dexter Tamio CHUN ,  Xavier Loic LELOUP ,  Laurent Rene MOLL

IPC: G11C11/4074 ,  G11C11/409

Abstract: Methods and apparatuses for to memories using dynamic voltage scaling are presented. The apparatus includes memory configured to communicate with a host. The memory includes a peripheral portion and a memory array. The memory is further configured to receive, from at least one power management circuit, a first supply voltage and a second supply voltage. The memory further includes a switch circuit. The switch circuit is configured to selectively provide the first supply voltage and the second supply voltage to the peripheral portion. The first supply voltage is static and has a first voltage range. The second supply voltage has a low second voltage range and a high second voltage range.

公开(公告)号：US20210064463A1

公开(公告)日：2021-03-04

申请号：US16944110

申请日：2020-07-30

Applicant: QUALCOMM Incorporated

Inventor： Jungwon SUH ,  Michael Hawjing LO ,  Dexter Tamio CHUN ,  Xavier Loic LELOUP ,  Laurent Rene MOLL

IPC: G06F11/10 ,  G06F3/06

Abstract: Methods and apparatuses for a system error-correcting code function are presented. The apparatus includes a memory configured to communicate with a host. The memory includes a memory array configured to store data. The memory is configured to provide the data stored in the memory array to the host in performing computing functions and configured to provide an error-correction code (ECC) associated with the data to the host. The ECC is not stored in the memory array in a first configuration of the memory and is stored in the memory array in a second configuration of the memory.

公开(公告)号：US20220350749A1

公开(公告)日：2022-11-03

申请号：US17244398

申请日：2021-04-29

Applicant: QUALCOMM INCORPORATED

Inventor： Alain ARTIERI ,  Rakesh Kumar GUPTA ,  Subbarao PALACHARLA ,  Kedar BHOLE ,  Laurent Rene MOLL ,  Carlo SPITALE ,  Sparsh SINGHAI ,  Shyamkumar THOZIYOOR ,  Gopi TUMMALA ,  Christophe AVOINNE ,  Samir GINDE ,  Syed Minhaj HASSAN ,  Jean-Jacques LECLER ,  Luigi VINCI

IPC: G06F12/0893 ,  G06F12/12

Abstract: Data caching may include storing data associated with DRAM transaction requests in data storage structures organized in a manner corresponding to the DRAM bank, bank group and rank organization. Data may be selected for transfer to the DRAM by selecting among the data storage structures.