公开(公告)号：US20240038672A1

公开(公告)日：2024-02-01

申请号：US17877156

申请日：2022-07-29

Applicant: QUALCOMM Incorporated

Inventor： Mahalingam NAGARAJAN ,  Vaishnav SRINIVAS ,  Nitin JUNEJA ,  Christophe AVOINNE ,  Xavier Loic LELOUP ,  Michael David JAGER ,  Charles David PAYNTER ,  Joon Young PARK

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/5386 ,  H01L25/0655 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/14132 ,  H01L24/81 ,  H01L2224/81815

Abstract: A package comprising a substrate comprising at least one dielectric layer and a plurality of interconnects; a first integrated device coupled to the substrate through a first plurality of solder interconnects, wherein the first plurality of solder interconnects includes a first plurality of inner solder interconnects and a first plurality of perimeter solder interconnects; and a second integrated device coupled to the substrate through a second plurality of solder interconnects. The first integrated device is configured to be electrically coupled to the second integrated device through an electrical path. The electrical path comprises an inner solder interconnect from the first plurality of inner solder interconnects, at least one interconnect from the plurality of interconnects, and a solder interconnect from the second plurality of solder interconnects.

公开(公告)号：US20220350749A1

公开(公告)日：2022-11-03

申请号：US17244398

申请日：2021-04-29

Applicant: QUALCOMM INCORPORATED

Inventor： Alain ARTIERI ,  Rakesh Kumar GUPTA ,  Subbarao PALACHARLA ,  Kedar BHOLE ,  Laurent Rene MOLL ,  Carlo SPITALE ,  Sparsh SINGHAI ,  Shyamkumar THOZIYOOR ,  Gopi TUMMALA ,  Christophe AVOINNE ,  Samir GINDE ,  Syed Minhaj HASSAN ,  Jean-Jacques LECLER ,  Luigi VINCI

IPC: G06F12/0893 ,  G06F12/12

Abstract: Data caching may include storing data associated with DRAM transaction requests in data storage structures organized in a manner corresponding to the DRAM bank, bank group and rank organization. Data may be selected for transfer to the DRAM by selecting among the data storage structures.

公开(公告)号：US20190012271A1

公开(公告)日：2019-01-10

申请号：US15641765

申请日：2017-07-05

Applicant: QUALCOMM Incorporated

Inventor： Christophe AVOINNE ,  Samar ASBE ,  Thomas ZENG ,  Jean-Louis TARDIEUX ,  Jeffrey SHABEL ,  Azzedine TOUZNI

IPC: G06F12/14 ,  G06F12/1027 ,  G06F12/1009 ,  G06F1/32

Abstract: One feature pertains to an apparatus that includes a memory circuit, a system memory-management unit (SMMU), and a processing circuit. The memory circuit stores an executable program associated with a client. The SMMU enforces memory access control policies for the memory circuit, and includes a plurality of micro-translation lookaside buffers (micro-TLBs), macro-TLB, and a page walker circuit. The plurality of micro-TLBs include a first micro-TLB that enforces memory access control policies for the client. The processing circuit loads memory address translations associated with the executable program into the first micro-TLB, and initiates isolation mode for the first micro-TLB causing communications between the first micro-TLB and the macro-TLB and between the first micro-TLB and the page walker circuit to be severed. The first micro-TLB continues to enforce memory access control policies for the client while in isolation mode.