公开(公告)号：US20240078202A1

公开(公告)日：2024-03-07

申请号：US17929946

申请日：2022-09-06

Applicant: QUALCOMM Incorporated

Inventor： Jungwon SUH ,  Pankaj DESHMUKH ,  Shyamkumar THOZIYOOR ,  Subbarao PALACHARLA

IPC: G06F13/16 ,  G06F12/06

CPC classification number: G06F13/1694 ,  G06F12/0623

Abstract: Various embodiments include methods for implementing flexible ranks in a memory system. Embodiments may include receiving, at a memory controller, a first memory access command and a first address at which to implement the first memory access command in a logical rank, generating, by the memory controller, a first signal configured to indicate to a first memory device of the logical rank to implement the first memory access command via a first partial channel, sending, from the memory controller, the first signal to the first memory device, generating, by the memory controller, a second signal configured to indicate to a second memory device of the logical rank that is different from the first memory device to implement the first memory access command via a second partial channel, and sending, from the memory controller, the second signal to the second memory device.

公开(公告)号：US20220350749A1

公开(公告)日：2022-11-03

申请号：US17244398

申请日：2021-04-29

Applicant: QUALCOMM INCORPORATED

Inventor： Alain ARTIERI ,  Rakesh Kumar GUPTA ,  Subbarao PALACHARLA ,  Kedar BHOLE ,  Laurent Rene MOLL ,  Carlo SPITALE ,  Sparsh SINGHAI ,  Shyamkumar THOZIYOOR ,  Gopi TUMMALA ,  Christophe AVOINNE ,  Samir GINDE ,  Syed Minhaj HASSAN ,  Jean-Jacques LECLER ,  Luigi VINCI

IPC: G06F12/0893 ,  G06F12/12

Abstract: Data caching may include storing data associated with DRAM transaction requests in data storage structures organized in a manner corresponding to the DRAM bank, bank group and rank organization. Data may be selected for transfer to the DRAM by selecting among the data storage structures.

公开(公告)号：US20240111424A1

公开(公告)日：2024-04-04

申请号：US18527713

申请日：2023-12-04

Applicant: QUALCOMM Incorporated

Inventor： Shyamkumar THOZIYOOR ,  Pankaj DESHMUKH ,  Jungwon SUH ,  Subbarao PALACHARLA

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0635 ,  G06F3/0679

Abstract: Various embodiments include methods and devices for reducing latency in pseudo channel based memory systems. Embodiments may include a first pseudo channel selection device configured to selectively communicatively connect one of a plurality of pseudo channels to a first input/output (IO), and a second pseudo channel selection device configured to selectively communicatively connect one of the plurality of pseudo channels to a second IO, in which the first pseudo channel selection device and the second pseudo channel selection device may be operable to communicatively connect a first pseudo channel of the plurality of pseudo channels to the first IO and to the second IO concurrently. Embodiments may include the pseudo channel based memory system configured to receive a memory access command targeting the first pseudo channel, and use a first pseudo channel data bus and a second pseudo channel data bus to implement the memory access command.

公开(公告)号：US20220027067A1

公开(公告)日：2022-01-27

申请号：US17494089

申请日：2021-10-05

Applicant: QUALCOMM Incorporated

Inventor： Jungwon SUH ,  Dexter Tamio CHUN ,  Michael Hawjing LO ,  Shyamkumar THOZIYOOR ,  Ravindra KUMAR

IPC: G06F3/06 ,  G06F12/0875

Abstract: Methods and apparatuses for improve data clock to reduce power consumption are presented. The apparatus includes a memory configured to receive a data clock from a host via a link and to synchronize the data clock with the host. The memory includes a clock tree buffer configured to toggle based on the data clock to capture write data or to output read data and a command decoder configured to detect a data clock suspend command while the data clock is synchronized between the host and the memory. The clock tree buffer is configured to disable toggling based on the data clock in response to the command decoder detecting the data clock suspend command. the host includes a memory controller configured to provide a data clock suspend command to the memory via the link while the data clock is synchronized between the host and the memory.

公开(公告)号：US20250028445A1

公开(公告)日：2025-01-23

申请号：US18354525

申请日：2023-07-18

Applicant: QUALCOMM Incorporated

Inventor： Pankaj DESHMUKH ,  Subbarao PALACHARLA ,  Shyamkumar THOZIYOOR ,  Jungwon SUH ,  Anurag NANNAKA

IPC: G06F3/06

Abstract: Various embodiments include systems and methods for improving the efficiency of a memory subsystem in a computing device. The memory subsystem may be configured to detect memory access events and determining their associated timings and determine an efficiency of the memory subsystem based on operational parameters of the memory subsystem, the detecting memory access events, and associated timings. The memory subsystem may adjust the operational parameters of the memory subsystem based on the determined efficiency of the memory subsystem. The memory subsystem may dynamically modify the operations of the memory subsystem based on the adjusted operational parameters.

公开(公告)号：US20230136996A1

公开(公告)日：2023-05-04

申请号：US17452606

申请日：2021-10-28

Applicant: QUALCOMM Incorporated

Inventor： Shyamkumar THOZIYOOR ,  Pankaj DESHMUKH ,  Jungwon SUH ,  Subbarao PALACHARLA

IPC: G06F3/06

Abstract: Various embodiments include methods and devices for reducing latency in pseudo channel based memory systems. Embodiments may include a first pseudo channel selection device configured to selectively communicatively connect one of a plurality of pseudo channels to a first input/output (IO), and a second pseudo channel selection device configured to selectively communicatively connect one of the plurality of pseudo channels to a second IO, in which the first pseudo channel selection device and the second pseudo channel selection device may be operable to communicatively connect a first pseudo channel of the plurality of pseudo channels to the first IO and to the second IO concurrently. Embodiments may include the pseudo channel based memory system configured to receive a memory access command targeting the first pseudo channel, and use a first pseudo channel data bus and a second pseudo channel data bus to implement the memory access command.

公开(公告)号：US20210133100A1

公开(公告)日：2021-05-06

申请号：US16823306

申请日：2020-03-18

Applicant: QUALCOMM INCORPORATED

Inventor： Alain ARTIERI ,  Jean-Jacques LECLER ,  Shyamkumar THOZIYOOR

IPC: G06F12/06 ,  G06F12/1018 ,  G06F12/0864 ,  G06F12/02

Abstract: Memory utilization in an SDRAM system may be improved by increasing memory bank group and memory bank interleaving. Memory bank group interleaving and memory bank interleaving may be increased by a memory controller generating a physical memory address in which the bank group address bits are positioned nearer the LSB of the physical memory address than the MSB. Alternatively, or in addition to positioning the bank group address bits in such a manner, memory bank group interleaving and memory bank interleaving may be increased by hashing the bank group address bits and bank address bits of the physical memory address with row address bits of the initial physical memory address, A rank address bit may also be involved in the hashing.