公开(公告)号：US20210382651A1

公开(公告)日：2021-12-09

申请号：US16894550

申请日：2020-06-05

Applicant: QUALCOMM Incorporated

Inventor： Jean-Jacques LECLER ,  Philippe BOUCARD

IPC: G06F3/06

Abstract: In some aspects, the present disclosure provides a method for scheduling transactions for a memory by a scheduler. The method includes receiving a plurality of transactions, each of the plurality of transactions being associated with a corresponding priority level. The method also includes selecting one or more transactions of the plurality of transactions that meet one or more constraints based on one or more past transactions scheduled for the memory by the scheduler. The method also includes determining whether at least one transaction of the one or more transactions satisfies a threshold priority level.

公开(公告)号：US20220019459A1

公开(公告)日：2022-01-20

申请号：US16933209

申请日：2020-07-20

Applicant: QUALCOMM Incorporated

Inventor： Jean-Jacques LECLER

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/54 ,  G06F9/50 ,  G06F13/362

Abstract: Aspects of the present disclosure provide techniques for controlling early responses in systems employing master devices and slave devices. An example method for controlling a slave device includes receiving a plurality of transaction requests from a master device for the slave device to execute and respond, determining whether a response criterion is met based on a number of the plurality of transaction requests that have been executed and a number of response messages transmitted to the master device for the plurality of transaction requests, while the response criterion is met, proceeding with transmitting response messages for the plurality of transaction requests, and while the response criterion is not met, refraining from transmitting response messages for any of the plurality of transaction requests.

公开(公告)号：US20210133100A1

公开(公告)日：2021-05-06

申请号：US16823306

申请日：2020-03-18

Applicant: QUALCOMM INCORPORATED

Inventor： Alain ARTIERI ,  Jean-Jacques LECLER ,  Shyamkumar THOZIYOOR

IPC: G06F12/06 ,  G06F12/1018 ,  G06F12/0864 ,  G06F12/02

Abstract: Memory utilization in an SDRAM system may be improved by increasing memory bank group and memory bank interleaving. Memory bank group interleaving and memory bank interleaving may be increased by a memory controller generating a physical memory address in which the bank group address bits are positioned nearer the LSB of the physical memory address than the MSB. Alternatively, or in addition to positioning the bank group address bits in such a manner, memory bank group interleaving and memory bank interleaving may be increased by hashing the bank group address bits and bank address bits of the physical memory address with row address bits of the initial physical memory address, A rank address bit may also be involved in the hashing.

公开(公告)号：US20220350749A1

公开(公告)日：2022-11-03

申请号：US17244398

申请日：2021-04-29

Applicant: QUALCOMM INCORPORATED

Inventor： Alain ARTIERI ,  Rakesh Kumar GUPTA ,  Subbarao PALACHARLA ,  Kedar BHOLE ,  Laurent Rene MOLL ,  Carlo SPITALE ,  Sparsh SINGHAI ,  Shyamkumar THOZIYOOR ,  Gopi TUMMALA ,  Christophe AVOINNE ,  Samir GINDE ,  Syed Minhaj HASSAN ,  Jean-Jacques LECLER ,  Luigi VINCI

IPC: G06F12/0893 ,  G06F12/12

Abstract: Data caching may include storing data associated with DRAM transaction requests in data storage structures organized in a manner corresponding to the DRAM bank, bank group and rank organization. Data may be selected for transfer to the DRAM by selecting among the data storage structures.