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    ERROR HANDLING FOR REPROJECTION TIMELINE
    1.
    发明申请
    ERROR HANDLING FOR REPROJECTION TIMELINE 有权

    公开(公告)号：US20240386980A1

    公开(公告)日：2024-11-21

    申请号：US18522098

    申请日：2023-11-28

    Applicant: QUALCOMM Incorporated

    Inventor： Simon Peter William BOOTH ,  Subbarao PALACHARLA ,  George PATSILARAS ,  Hiral NANDU ,  Girish BHAT ,  Yen-Kuan WU

    IPC: G11C29/12

    Abstract: Aspects presented herein relate to methods and devices for data or graphics processing including an apparatus, e.g., a graphics processing unit (GPU). The apparatus may obtain an indication of a data write for data associated with data processing. The apparatus may write, based on the indication, the data associated with the data processing to a memory address. The apparatus may receive a read request for the data including the memory address, where the read request is associated with a read with invalidate process. The apparatus may retrieve, based on the read request, the data from at least one of a first cache or at least one second memory, where the retrieval of the data is based on a timing of the indication of the data write. The apparatus may output the retrieved data from at least one of the first cache or the at least one second memory.

    Flexible Dual Ranks Memory System To Boost Performance
    2.
    发明公开
    Flexible Dual Ranks Memory System To Boost Performance 审中-公开

    公开(公告)号：US20240078202A1

    公开(公告)日：2024-03-07

    申请号：US17929946

    申请日：2022-09-06

    Applicant: QUALCOMM Incorporated

    Inventor： Jungwon SUH ,  Pankaj DESHMUKH ,  Shyamkumar THOZIYOOR ,  Subbarao PALACHARLA

    IPC: G06F13/16 ,  G06F12/06

    CPC classification number: G06F13/1694 ,  G06F12/0623

    Abstract: Various embodiments include methods for implementing flexible ranks in a memory system. Embodiments may include receiving, at a memory controller, a first memory access command and a first address at which to implement the first memory access command in a logical rank, generating, by the memory controller, a first signal configured to indicate to a first memory device of the logical rank to implement the first memory access command via a first partial channel, sending, from the memory controller, the first signal to the first memory device, generating, by the memory controller, a second signal configured to indicate to a second memory device of the logical rank that is different from the first memory device to implement the first memory access command via a second partial channel, and sending, from the memory controller, the second signal to the second memory device.

    Self-Characterizing, Evaluating, and Adaptive High Performance Memory Controller
    3.
    发明申请
    Self-Characterizing, Evaluating, and Adaptive High Performance Memory Controller 有权

    公开(公告)号：US20250028445A1

    公开(公告)日：2025-01-23

    申请号：US18354525

    申请日：2023-07-18

    Applicant: QUALCOMM Incorporated

    Inventor： Pankaj DESHMUKH ,  Subbarao PALACHARLA ,  Shyamkumar THOZIYOOR ,  Jungwon SUH ,  Anurag NANNAKA

    IPC: G06F3/06

    Abstract: Various embodiments include systems and methods for improving the efficiency of a memory subsystem in a computing device. The memory subsystem may be configured to detect memory access events and determining their associated timings and determine an efficiency of the memory subsystem based on operational parameters of the memory subsystem, the detecting memory access events, and associated timings. The memory subsystem may adjust the operational parameters of the memory subsystem based on the determined efficiency of the memory subsystem. The memory subsystem may dynamically modify the operations of the memory subsystem based on the adjusted operational parameters.

    Reducing Latency In Pseudo Channel Based Memory Systems
    4.
    发明申请
    Reducing Latency In Pseudo Channel Based Memory Systems 有权

    公开(公告)号：US20230136996A1

    公开(公告)日：2023-05-04

    申请号：US17452606

    申请日：2021-10-28

    Applicant: QUALCOMM Incorporated

    Inventor： Shyamkumar THOZIYOOR ,  Pankaj DESHMUKH ,  Jungwon SUH ,  Subbarao PALACHARLA

    IPC: G06F3/06

    Abstract: Various embodiments include methods and devices for reducing latency in pseudo channel based memory systems. Embodiments may include a first pseudo channel selection device configured to selectively communicatively connect one of a plurality of pseudo channels to a first input/output (IO), and a second pseudo channel selection device configured to selectively communicatively connect one of the plurality of pseudo channels to a second IO, in which the first pseudo channel selection device and the second pseudo channel selection device may be operable to communicatively connect a first pseudo channel of the plurality of pseudo channels to the first IO and to the second IO concurrently. Embodiments may include the pseudo channel based memory system configured to receive a memory access command targeting the first pseudo channel, and use a first pseudo channel data bus and a second pseudo channel data bus to implement the memory access command.

    PHYSICAL ADDRESS BASED SET PARTITIONING
    7.
    发明申请
    PHYSICAL ADDRESS BASED SET PARTITIONING 有权

    公开(公告)号：US20240370376A1

    公开(公告)日：2024-11-07

    申请号：US18522049

    申请日：2023-11-28

    Applicant: QUALCOMM Incorporated

    Inventor： Subbarao PALACHARLA ,  Hiral NANDU ,  George PATSILARAS ,  Simon Peter William BOOTH ,  Rakesh Kumar GUPTA ,  Kedar BHOLE

    IPC: G06F12/0888

    Abstract: Aspects presented herein relate to methods and devices for data or graphics processing including an apparatus, e.g., a graphics processing unit (GPU). The apparatus may configure an address range in a cache. The apparatus may also obtain a request to access data in the cache, where the request to access the data includes an address in the cache that maps to a set index in a plurality of set indexes, where an address value for the set index corresponds to a portion of the address. Further, the apparatus may select an updated address value for the set index, where the updated address value is associated with an updated address within the address range, and the updated address value corresponds to a portion of the updated address. The apparatus may also allocate the data in the request to the updated address value for the set index.

    REDUCING LATENCY IN PSEUDO CHANNEL BASED MEMORY SYSTEMS
    8.
    发明公开
    REDUCING LATENCY IN PSEUDO CHANNEL BASED MEMORY SYSTEMS 审中-公开

    公开(公告)号：US20240111424A1

    公开(公告)日：2024-04-04

    申请号：US18527713

    申请日：2023-12-04

    Applicant: QUALCOMM Incorporated

    Inventor： Shyamkumar THOZIYOOR ,  Pankaj DESHMUKH ,  Jungwon SUH ,  Subbarao PALACHARLA

    IPC: G06F3/06

    CPC classification number: G06F3/0611 ,  G06F3/0635 ,  G06F3/0679

    Abstract: Various embodiments include methods and devices for reducing latency in pseudo channel based memory systems. Embodiments may include a first pseudo channel selection device configured to selectively communicatively connect one of a plurality of pseudo channels to a first input/output (IO), and a second pseudo channel selection device configured to selectively communicatively connect one of the plurality of pseudo channels to a second IO, in which the first pseudo channel selection device and the second pseudo channel selection device may be operable to communicatively connect a first pseudo channel of the plurality of pseudo channels to the first IO and to the second IO concurrently. Embodiments may include the pseudo channel based memory system configured to receive a memory access command targeting the first pseudo channel, and use a first pseudo channel data bus and a second pseudo channel data bus to implement the memory access command.

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