公开(公告)号：US20150277536A1

公开(公告)日：2015-10-01

申请号：US14266642

申请日：2014-04-30

Applicant: Qualcomm Incorporated

Inventor： KRISHNA V.S.S.S.R VANKA ,  HEE JUN PARK ,  SRAVAN KUMAR AMBAPURAM ,  SHIRISH KUMAR AGARWAL

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/329 ,  H04W52/0251 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D70/1262 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/164

Abstract: Systems and methods for dynamically adjusting an input parameter to a power domain in a portable computing device are disclosed. The power domain includes two or more processing resources that share a power source. Dynamic use of the two or more processing resources creates an opportunity to adjust the input parameter when a status change associated with a processing resource in the power domain occurs. A controller in the power domain includes logic that responds to a status indicator associated with a respective processing resource in the power domain by generating a control signal that directs a device to adjust one or both of input voltage and clock frequency.

Abstract translation: 公开了用于在便携式计算设备中动态调整输入参数到电力域的系统和方法。 功率域包括共享电源的两个或更多个处理资源。 当与功率域中的处理资源相关联的状态变化发生时，两个或多个处理资源的动态使用产生调整输入参数的机会。 功率域中的控制器包括通过产生引导设备调整输入电压和时钟频率中的一个或两者的控制信号来响应与功率域中的相应处理资源相关联的状态指示符的逻辑。

公开(公告)号：US20150261583A1

公开(公告)日：2015-09-17

申请号：US14210064

申请日：2014-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： KRISHNA VSSSR VANKA ,  SHIRISH KUMAR AGARWAL ,  SRAVAN KUMAR AMBAPURAM

IPC: G06F9/54

CPC classification number: G06F9/54 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/544

Abstract: Systems and methods that allow for Dynamic Clock and Voltage Scaling (DCVS) aware interprocessor communications among processors such as those used in or with a portable computing device (“PCD”) are presented. During operation of the PCD at least one data packet is received at a first processing component. Additionally, the first processing component also receives workload information about a second processing component operating under dynamic clock and voltage scaling (DCVS). A determination is made, based at least in part on the received workload information, whether to send the at least one data packet from the first processing component to the second processing component or to a buffer, providing a cost effective ability to reduce power consumption and improved battery life in PCDs with multi-cores or multi-CPUs implementing DCVS algorithms or logic.

Abstract translation: 提供了允许处理器之间的动态时钟和电压调节（DCVS）感知处理器间通信的系统和方法，例如在便携式计算设备（“PCD”）中使用的处理器之间的处理器间通信。 在PCD的操作期间，在第一处理组件处接收至少一个数据分组。 此外，第一处理组件还接收关于在动态时钟和电压缩放（DCVS）下操作的第二处理组件的工作负载信息。 至少部分地基于所接收的工作负载信息，确定是否将所述至少一个数据分组从第一处理组件发送到第二处理组件或缓冲器，提供降低功耗的成本有效的能力，以及 提高了使用多核或多CPU实现DCVS算法或逻辑的PCD的电池寿命。

公开(公告)号：US20160203083A1

公开(公告)日：2016-07-14

申请号：US14595998

申请日：2015-01-13

Applicant: QUALCOMM INCORPORATED

Inventor： HEE JUN PARK ,  KRISHNA VSSSR VANKA ,  SRAVAN KUMAR AMBAPURAM ,  SHIRISH KUMAR AGARWAL ,  ASHVINKUMAR NAMJOSHI ,  HARSHAD BHUTADA

IPC: G06F12/08

CPC classification number: G06F12/084 ,  G06F9/4856 ,  G06F9/5016 ,  G06F11/34 ,  G06F11/3433 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0833 ,  G06F12/0842 ,  G06F2212/1021 ,  G06F2212/1028 ,  G06F2212/601 ,  Y02D10/13

Abstract: A dynamic cache extension in a multi-cluster heterogeneous processor architecture is described. One embodiment is a system comprising a first processor cluster having a first level two (L2) cache and a second processor cluster having a second L2 cache. The system further comprises a controller in communication with the first and second L2 caches. The controller receives a processor workload input and a cache workload input from the first processor cluster. Based on processor workload input and the cache workload input, the cache controller determines whether a current task associated with the first processor cluster is limited by a size threshold of the first L2 cache or a performance threshold of the first processor cluster. If the current task is limited by the size threshold of the first L2 cache, the controller uses at least a portion of the second L2 cache as an extension of the first L2 cache.

Abstract translation: 描述了多集群异构处理器架构中的动态缓存扩展。 一个实施例是包括具有第一级二（L2）高速缓存的第一处理器集群和具有第二L2高速缓存的第二处理器集群的系统。 该系统还包括与第一和第二L2高速缓存通信的控制器。 控制器从第一处理器集群接收处理器工作负载输入和高速缓存工作负载输入。 基于处理器工作负载输入和缓存工作负荷输入，高速缓存控制器确定与第一处理器集群相关联的当前任务是否受到第一L2高速缓存的大小阈值或第一处理器集群的性能阈值的限制。 如果当前任务受到第一L2高速缓存的大小阈值的限制，则控制器使用第二L2高速缓存的至少一部分作为第一L2高速缓存的扩展。

公开(公告)号：US20160124778A1

公开(公告)日：2016-05-05

申请号：US14993991

申请日：2016-01-12

Applicant: QUALCOMM INCORPORATED

Inventor： KRISHNA VSSSR VANKA ,  SHIRISH KUMAR AGARWAL ,  SRAVAN KUMAR AMBAPURAM

IPC: G06F9/54 ,  G06F1/32

CPC classification number: G06F9/54 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/544

Abstract: Systems and methods that allow for Dynamic Clock and Voltage Scaling (DCVS) aware interprocessor communications among processors such as those used in or with a portable computing device (“PCD”) are presented. During operation of the PCD at least one data packet is received at a first processing component. Additionally, the first processing component also receives workload information about a second processing component operating under dynamic clock and voltage scaling (DCVS). A determination is made, based at least in part on the received workload information, whether to send the at least one data packet from the first processing component to the second processing component or to a buffer, providing a cost effective ability to reduce power consumption and improved battery life in PCDs with multi-cores or multi-CPUs implementing DCVS algorithms or logic.

公开(公告)号：US20150370316A1

公开(公告)日：2015-12-24

申请号：US14839836

申请日：2015-08-28

Applicant: Qualcomm Incorporated

Inventor： HEE JUN PARK ,  KRISHNA V.S.S.S.R. VANKA ,  SRAVAN KUMAR AMBAPURAM ,  SHIRISH KUMAR AGARWAL ,  SHIH-HSIN JASON HU

IPC: G06F1/32 ,  H04W52/02

CPC classification number: G06F1/3296 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/329 ,  H04W52/0251 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D70/1262 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/164

Abstract: Systems and methods for dynamically adjusting an input parameter, such as power supply level, to a shared power domain in a portable computing device are disclosed. The power domain includes a plurality of processing resources that share the power source. The power supply level is reduced based on a critical core vote pool derived from votes from the plurality of processing resources. The critical core vote pool is narrowed from all the votes by disqualifying votes based on the operating status of the associated processing resources. For example, because inactive processing resources may be unaffected by a change in the voltage level to the shared domain, and because certain active processing resources are in a position to adjust to a power change dictated by another processing resource, such processing resources may be considered noncritical and their votes disqualified from consideration.

Abstract translation: 公开了一种将便携式计算设备中的共享电力域动态调整输入参数（例如电源电平）的系统和方法。 功率域包括共享电源的多个处理资源。 基于来自多个处理资源的投票的关键核心投票池，电力供应水平被减少。 基于相关处理资源的运作状况，通过取消投票资格，所有投票的关键核心投票池缩小。 例如，由于非活动处理资源可能不受到对共享域的电压电平的改变的影响，并且由于某些活动处理资源处于能够调整到另一个处理资源所规定的功率变化的位置，因此可以考虑这样的处理资源 不重要，其选票不合格。